SRS Standard pair #487086569

details

property	value
status	complete
benchmark	214183.xml
ran by	Akihisa Yamada
cpu timeout	1200 seconds
wallclock timeout	300 seconds
memory limit	137438953472 bytes
execution host	n141.star.cs.uiowa.edu
space	ICFP_2010

run statistics

property	value
solver	MultumNonMulta 20 June 2020 20G sparse
configuration	default
runtime (wallclock)	3.53448 seconds
cpu usage	12.703
user time	11.0702
system time	1.63284
max virtual memory	5.1232048E7
max residence set size	1223084.0

stage attributes

key	value
starexec-result	YES

output

YES

After renaming modulo { 0->0, 1->1, 2->2, 3->3, 4->4, 5->5 }, 
it remains to prove termination of the 50-rule system
{ 0 0 1 2 -> 2 3 1 0 0 ,
  0 0 1 2 -> 3 1 0 0 2 ,
  0 0 1 2 -> 0 0 2 3 1 1 ,
  0 1 0 4 -> 3 1 4 0 0 ,
  0 1 0 4 -> 3 4 0 0 3 1 ,
  0 1 0 4 -> 4 3 1 0 5 0 ,
  0 1 0 4 -> 5 0 4 3 1 0 ,
  0 1 0 5 -> 3 5 3 1 0 0 ,
  0 1 0 5 -> 5 3 1 0 0 2 ,
  0 1 4 2 -> 2 3 1 4 0 ,
  0 1 4 2 -> 4 0 3 1 2 4 ,
  0 1 4 2 -> 4 3 1 1 0 2 ,
  0 5 0 4 -> 4 0 0 3 5 ,
  0 5 0 4 -> 5 0 0 3 4 ,
  0 5 0 5 -> 3 5 2 0 0 5 ,
  0 5 0 5 -> 5 3 5 4 0 0 ,
  0 5 0 5 -> 5 5 3 4 0 0 ,
  2 0 1 2 -> 0 2 4 1 2 ,
  2 0 1 2 -> 2 5 0 2 2 1 ,
  2 0 1 2 -> 3 1 3 2 2 0 ,
  2 0 4 2 -> 4 0 2 2 1 ,
  2 0 4 2 -> 4 0 2 1 2 1 ,
  2 0 5 2 -> 0 2 1 5 2 2 ,
  3 0 4 2 -> 0 3 4 1 1 2 ,
  3 0 4 2 -> 4 3 3 1 0 2 ,
  0 0 1 2 2 -> 0 0 2 1 2 1 ,
  0 0 1 3 2 -> 0 3 1 2 0 4 ,
  0 0 1 3 2 -> 2 5 0 3 1 0 ,
  0 0 5 2 2 -> 0 0 2 5 2 1 ,
  0 1 0 5 2 -> 0 2 1 0 3 5 ,
  0 1 0 5 5 -> 1 3 5 0 0 5 ,
  0 1 2 0 5 -> 4 0 5 2 1 0 ,
  0 1 3 0 4 -> 1 0 3 4 4 0 ,
  0 1 3 4 2 -> 4 2 1 0 3 4 ,
  0 1 4 2 2 -> 1 1 0 2 4 2 ,
  0 1 4 2 4 -> 4 0 2 3 1 4 ,
  0 1 4 3 2 -> 3 1 2 0 4 4 ,
  0 3 0 0 5 -> 5 3 1 0 0 0 ,
  0 4 1 0 4 -> 4 0 2 1 4 0 ,
  0 4 3 2 2 -> 4 2 0 3 5 2 ,
  0 5 1 0 4 -> 5 2 4 1 0 0 ,
  0 5 1 4 2 -> 4 0 3 5 1 2 ,
  2 1 0 1 2 -> 2 1 1 0 2 3 ,
  2 4 0 5 2 -> 0 4 2 3 5 2 ,
  3 0 0 1 2 -> 0 3 5 1 0 2 ,
  3 0 0 5 2 -> 2 0 0 3 5 1 ,
  3 0 5 4 2 -> 4 0 3 5 2 1 ,
  3 2 0 1 2 -> 2 1 3 1 0 2 ,
  3 2 0 5 2 -> 2 0 2 3 4 5 ,
  3 2 0 5 2 -> 5 3 0 2 2 2 }


The system was reversed.

After renaming modulo { 2->0, 1->1, 0->2, 3->3, 4->4, 5->5 }, 
it remains to prove termination of the 50-rule system
{ 0 1 2 2 -> 2 2 1 3 0 ,
  0 1 2 2 -> 0 2 2 1 3 ,
  0 1 2 2 -> 1 1 3 0 2 2 ,
  4 2 1 2 -> 2 2 4 1 3 ,
  4 2 1 2 -> 1 3 2 2 4 3 ,
  4 2 1 2 -> 2 5 2 1 3 4 ,
  4 2 1 2 -> 2 1 3 4 2 5 ,
  5 2 1 2 -> 2 2 1 3 5 3 ,
  5 2 1 2 -> 0 2 2 1 3 5 ,
  0 4 1 2 -> 2 4 1 3 0 ,
  0 4 1 2 -> 4 0 1 3 2 4 ,
  0 4 1 2 -> 0 2 1 1 3 4 ,
  4 2 5 2 -> 5 3 2 2 4 ,
  4 2 5 2 -> 4 3 2 2 5 ,
  5 2 5 2 -> 5 2 2 0 5 3 ,
  5 2 5 2 -> 2 2 4 5 3 5 ,
  5 2 5 2 -> 2 2 4 3 5 5 ,
  0 1 2 0 -> 0 1 4 0 2 ,
  0 1 2 0 -> 1 0 0 2 5 0 ,
  0 1 2 0 -> 2 0 0 3 1 3 ,
  0 4 2 0 -> 1 0 0 2 4 ,
  0 4 2 0 -> 1 0 1 0 2 4 ,
  0 5 2 0 -> 0 0 5 1 0 2 ,
  0 4 2 3 -> 0 1 1 4 3 2 ,
  0 4 2 3 -> 0 2 1 3 3 4 ,
  0 0 1 2 2 -> 1 0 1 0 2 2 ,
  0 3 1 2 2 -> 4 2 0 1 3 2 ,
  0 3 1 2 2 -> 2 1 3 2 5 0 ,
  0 0 5 2 2 -> 1 0 5 0 2 2 ,
  0 5 2 1 2 -> 5 3 2 1 0 2 ,
  5 5 2 1 2 -> 5 2 2 5 3 1 ,
  5 2 0 1 2 -> 2 1 0 5 2 4 ,
  4 2 3 1 2 -> 2 4 4 3 2 1 ,
  0 4 3 1 2 -> 4 3 2 1 0 4 ,
  0 0 4 1 2 -> 0 4 0 2 1 1 ,
  4 0 4 1 2 -> 4 1 3 0 2 4 ,
  0 3 4 1 2 -> 4 4 2 0 1 3 ,
  5 2 2 3 2 -> 2 2 2 1 3 5 ,
  4 2 1 4 2 -> 2 4 1 0 2 4 ,
  0 0 3 4 2 -> 0 5 3 2 0 4 ,

popout

output may be truncated. 'popout' for the full output.

job log

popout

actions all output return to SRS Standard