details

property	value
status	complete
benchmark	27235.xml
ran by	Akihisa Yamada
cpu timeout	1200 seconds
wallclock timeout	300 seconds
memory limit	137438953472 bytes
execution host	n138.star.cs.uiowa.edu
space	ICFP_2010

run statistics

property	value
solver	MultumNonMulta 20 June 2020 20G sparse
configuration	default
runtime (wallclock)	3.74554 seconds
cpu usage	13.3867
user time	12.8034
system time	0.583289
max virtual memory	2.5864528E7
max residence set size	1244312.0

stage attributes

key	value
starexec-result	YES

output

YES After renaming modulo { 0->0, 1->1, 2->2 }, it remains to prove termination of the 16-rule system { 0 1 2 1 -> 1 2 1 1 0 1 2 0 1 2 , 0 1 2 1 -> 1 2 1 1 0 1 2 0 1 2 0 1 2 , 0 1 2 1 -> 1 2 1 1 0 1 2 0 1 2 0 1 2 0 1 2 , 0 1 2 1 -> 1 2 1 1 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 , 0 1 2 1 -> 1 2 1 1 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 , 0 1 2 1 -> 1 2 1 1 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 , 0 1 2 1 -> 1 2 1 1 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 , 0 1 2 1 -> 1 2 1 1 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 , 0 1 2 1 -> 1 2 1 1 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 , 0 1 2 1 -> 1 2 1 1 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 , 0 1 2 1 -> 1 2 1 1 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 , 0 1 2 1 -> 1 2 1 1 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 , 0 1 2 1 -> 1 2 1 1 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 , 0 1 2 1 -> 1 2 1 1 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 , 0 1 2 1 -> 1 2 1 1 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 , 0 1 2 1 -> 1 2 1 1 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 } The system was reversed. After renaming modulo { 1->0, 2->1, 0->2 }, it remains to prove termination of the 16-rule system { 0 1 0 2 -> 1 0 2 1 0 2 0 0 1 0 , 0 1 0 2 -> 1 0 2 1 0 2 1 0 2 0 0 1 0 , 0 1 0 2 -> 1 0 2 1 0 2 1 0 2 1 0 2 0 0 1 0 , 0 1 0 2 -> 1 0 2 1 0 2 1 0 2 1 0 2 1 0 2 0 0 1 0 , 0 1 0 2 -> 1 0 2 1 0 2 1 0 2 1 0 2 1 0 2 1 0 2 0 0 1 0 , 0 1 0 2 -> 1 0 2 1 0 2 1 0 2 1 0 2 1 0 2 1 0 2 1 0 2 0 0 1 0 , 0 1 0 2 -> 1 0 2 1 0 2 1 0 2 1 0 2 1 0 2 1 0 2 1 0 2 1 0 2 0 0 1 0 , 0 1 0 2 -> 1 0 2 1 0 2 1 0 2 1 0 2 1 0 2 1 0 2 1 0 2 1 0 2 1 0 2 0 0 1 0 , 0 1 0 2 -> 1 0 2 1 0 2 1 0 2 1 0 2 1 0 2 1 0 2 1 0 2 1 0 2 1 0 2 1 0 2 0 0 1 0 , 0 1 0 2 -> 1 0 2 1 0 2 1 0 2 1 0 2 1 0 2 1 0 2 1 0 2 1 0 2 1 0 2 1 0 2 1 0 2 0 0 1 0 , 0 1 0 2 -> 1 0 2 1 0 2 1 0 2 1 0 2 1 0 2 1 0 2 1 0 2 1 0 2 1 0 2 1 0 2 1 0 2 1 0 2 0 0 1 0 , 0 1 0 2 -> 1 0 2 1 0 2 1 0 2 1 0 2 1 0 2 1 0 2 1 0 2 1 0 2 1 0 2 1 0 2 1 0 2 1 0 2 1 0 2 0 0 1 0 , 0 1 0 2 -> 1 0 2 1 0 2 1 0 2 1 0 2 1 0 2 1 0 2 1 0 2 1 0 2 1 0 2 1 0 2 1 0 2 1 0 2 1 0 2 1 0 2 0 0 1 0 , 0 1 0 2 -> 1 0 2 1 0 2 1 0 2 1 0 2 1 0 2 1 0 2 1 0 2 1 0 2 1 0 2 1 0 2 1 0 2 1 0 2 1 0 2 1 0 2 1 0 2 0 0 1 0 , 0 1 0 2 -> 1 0 2 1 0 2 1 0 2 1 0 2 1 0 2 1 0 2 1 0 2 1 0 2 1 0 2 1 0 2 1 0 2 1 0 2 1 0 2 1 0 2 1 0 2 1 0 2 0 0 1 0 , 0 1 0 2 -> 1 0 2 1 0 2 1 0 2 1 0 2 1 0 2 1 0 2 1 0 2 1 0 2 1 0 2 1 0 2 1 0 2 1 0 2 1 0 2 1 0 2 1 0 2 1 0 2 1 0 2 0 0 1 0 } Applying sparse 2-tiling [Hofbauer/Geser/Waldmann, FSCD 2019]. After renaming modulo { (0,0)->0, (0,1)->1, (1,0)->2, (0,2)->3, (2,0)->4, (2,1)->5, (1,1)->6 }, it remains to prove termination of the 96-rule system { 0 1 2 3 4 -> 1 2 3 5 2 3 4 0 1 2 0 , 0 1 2 3 5 -> 1 2 3 5 2 3 4 0 1 2 1 , 2 1 2 3 4 -> 6 2 3 5 2 3 4 0 1 2 0 , 2 1 2 3 5 -> 6 2 3 5 2 3 4 0 1 2 1 , 4 1 2 3 4 -> 5 2 3 5 2 3 4 0 1 2 0 , 4 1 2 3 5 -> 5 2 3 5 2 3 4 0 1 2 1 , 0 1 2 3 4 -> 1 2 3 5 2 3 5 2 3 4 0 1 2 0 , 0 1 2 3 5 -> 1 2 3 5 2 3 5 2 3 4 0 1 2 1 , 2 1 2 3 4 -> 6 2 3 5 2 3 5 2 3 4 0 1 2 0 , 2 1 2 3 5 -> 6 2 3 5 2 3 5 2 3 4 0 1 2 1 , 4 1 2 3 4 -> 5 2 3 5 2 3 5 2 3 4 0 1 2 0 , 4 1 2 3 5 -> 5 2 3 5 2 3 5 2 3 4 0 1 2 1 , 0 1 2 3 4 -> 1 2 3 5 2 3 5 2 3 5 2 3 4 0 1 2 0 , 0 1 2 3 5 -> 1 2 3 5 2 3 5 2 3 5 2 3 4 0 1 2 1 , 2 1 2 3 4 -> 6 2 3 5 2 3 5 2 3 5 2 3 4 0 1 2 0 , 2 1 2 3 5 -> 6 2 3 5 2 3 5 2 3 5 2 3 4 0 1 2 1 , 4 1 2 3 4 -> 5 2 3 5 2 3 5 2 3 5 2 3 4 0 1 2 0 , 4 1 2 3 5 -> 5 2 3 5 2 3 5 2 3 5 2 3 4 0 1 2 1 , 0 1 2 3 4 -> 1 2 3 5 2 3 5 2 3 5 2 3 5 2 3 4 0 1 2 0 , 0 1 2 3 5 -> 1 2 3 5 2 3 5 2 3 5 2 3 5 2 3 4 0 1 2 1 , 2 1 2 3 4 -> 6 2 3 5 2 3 5 2 3 5 2 3 5 2 3 4 0 1 2 0 , 2 1 2 3 5 -> 6 2 3 5 2 3 5 2 3 5 2 3 5 2 3 4 0 1 2 1 , 4 1 2 3 4 -> 5 2 3 5 2 3 5 2 3 5 2 3 5 2 3 4 0 1 2 0 , 4 1 2 3 5 -> 5 2 3 5 2 3 5 2 3 5 2 3 5 2 3 4 0 1 2 1 , 0 1 2 3 4 -> 1 2 3 5 2 3 5 2 3 5 2 3 5 2 3 5 2 3 4 0 1 2 0 , 0 1 2 3 5 -> 1 2 3 5 2 3 5 2 3 5 2 3 5 2 3 5 2 3 4 0 1 2 1 , 2 1 2 3 4 -> 6 2 3 5 2 3 5 2 3 5 2 3 5 2 3 5 2 3 4 0 1 2 0 , 2 1 2 3 5 -> 6 2 3 5 2 3 5 2 3 5 2 3 5 2 3 5 2 3 4 0 1 2 1 , 4 1 2 3 4 -> 5 2 3 5 2 3 5 2 3 5 2 3 5 2 3 5 2 3 4 0 1 2 0 , 4 1 2 3 5 -> 5 2 3 5 2 3 5 2 3 5 2 3 5 2 3 5 2 3 4 0 1 2 1 , 0 1 2 3 4 -> 1 2 3 5 2 3 5 2 3 5 2 3 5 2 3 5 2 3 5 2 3 4 0 1 2 0 , 0 1 2 3 5 -> 1 2 3 5 2 3 5 2 3 5 2 3 5 2 3 5 2 3 5 2 3 4 0 1 2 1 , 2 1 2 3 4 -> 6 2 3 5 2 3 5 2 3 5 2 3 5 2 3 5 2 3 5 2 3 4 0 1 2 0 , 2 1 2 3 5 -> 6 2 3 5 2 3 5 2 3 5 2 3 5 2 3 5 2 3 5 2 3 4 0 1 2 1 , 4 1 2 3 4 -> 5 2 3 5 2 3 5 2 3 5 2 3 5 2 3 5 2 3 5 2 3 4 0 1 2 0 , 4 1 2 3 5 -> 5 2 3 5 2 3 5 2 3 5 2 3 5 2 3 5 2 3 5 2 3 4 0 1 2 1 , 0 1 2 3 4 -> 1 2 3 5 2 3 5 2 3 5 2 3 5 2 3 5 2 3 5 2 3 5 2 3 4 0 1 2 0 , 0 1 2 3 5 -> 1 2 3 5 2 3 5 2 3 5 2 3 5 2 3 5 2 3 5 2 3 5 2 3 4 0 1 2 1 , 2 1 2 3 4 -> 6 2 3 5 2 3 5 2 3 5 2 3 5 2 3 5 2 3 5 2 3 5 2 3 4 0 1 2 0 , 2 1 2 3 5 -> 6 2 3 5 2 3 5 2 3 5 2 3 5 2 3 5 2 3 5 2 3 5 2 3 4 0 1 2 1 , 4 1 2 3 4 -> 5 2 3 5 2 3 5 2 3 5 2 3 5 2 3 5 2 3 5 2 3 5 2 3 4 0 1 2 0 , 4 1 2 3 5 -> 5 2 3 5 2 3 5 2 3 5 2 3 5 2 3 5 2 3 5 2 3 5 2 3 4 0 1 2 1 , 0 1 2 3 4 -> 1 2 3 5 2 3 5 2 3 5 2 3 5 2 3 5 2 3 5 2 3 5 2 3 5 2 3 4 0 1 2 0 , 0 1 2 3 5 -> 1 2 3 5 2 3 5 2 3 5 2 3 5 2 3 5 2 3 5 2 3 5 2 3 5 2 3 4 0 1 2 1 , 2 1 2 3 4 -> 6 2 3 5 2 3 5 2 3 5 2 3 5 2 3 5 2 3 5 2 3 5 2 3 5 2 3 4 0 1 2 0 , 2 1 2 3 5 -> 6 2 3 5 2 3 5 2 3 5 2 3 5 2 3 5 2 3 5 2 3 5 2 3 5 2 3 4 0 1 2 1 , 4 1 2 3 4 -> 5 2 3 5 2 3 5 2 3 5 2 3 5 2 3 5 2 3 5 2 3 5 2 3 5 2 3 4 0 1 2 0 , 4 1 2 3 5 -> 5 2 3 5 2 3 5 2 3 5 2 3 5 2 3 5 2 3 5 2 3 5 2 3 5 2 3 4 0 1 2 1 , 0 1 2 3 4 -> 1 2 3 5 2 3 5 2 3 5 2 3 5 2 3 5 2 3 5 2 3 5 2 3 5 2 3 5 2 3 4 0 1 2 0 , 0 1 2 3 5 -> 1 2 3 5 2 3 5 2 3 5 2 3 5 2 3 5 2 3 5 2 3 5 2 3 5 2 3 5 2 3 4 0 1 2 1 , 2 1 2 3 4 -> 6 2 3 5 2 3 5 2 3 5 2 3 5 2 3 5 2 3 5 2 3 5 2 3 5 2 3 5 2 3 4 0 1 2 0 , 2 1 2 3 5 -> 6 2 3 5 2 3 5 2 3 5 2 3 5 2 3 5 2 3 5 2 3 5 2 3 5 2 3 5 2 3 4 0 1 2 1 , popout

output may be truncated. 'popout' for the full output.

job log

popout

actions

all output return to SRS Standard