details

property	value
status	complete
benchmark	z072.xml
ran by	Akihisa Yamada
cpu timeout	1200 seconds
wallclock timeout	300 seconds
memory limit	137438953472 bytes
execution host	n141.star.cs.uiowa.edu
space	Zantema_04

run statistics

property	value
solver	AProVE
configuration	standard
runtime (wallclock)	2.01495 seconds
cpu usage	3.50203
user time	3.32926
system time	0.172766
max virtual memory	1.8676996E7
max residence set size	255164.0

stage attributes

key	value
starexec-result	YES

output

YES proof of /export/starexec/sandbox/benchmark/theBenchmark.xml # AProVE Commit ID: 794c25de1cacf0d048858bcd21c9a779e1221865 marcel 20200619 unpublished dirty Termination w.r.t. Q of the given QTRS could be proven: (0) QTRS (1) RFCMatchBoundsTRSProof [EQUIVALENT, 0 ms] (2) YES ---------------------------------------- (0) Obligation: Q restricted rewrite system: The TRS R consists of the following rules: a(l(x1)) -> l(a(x1)) r(a(a(x1))) -> a(a(r(x1))) b(l(x1)) -> b(a(r(x1))) r(b(x1)) -> l(b(x1)) Q is empty. ---------------------------------------- (1) RFCMatchBoundsTRSProof (EQUIVALENT) Termination of the TRS R could be shown with a Match Bound [MATCHBOUNDS1,MATCHBOUNDS2] of 3. This implies Q-termination of R. The following rules were used to construct the certificate: a(l(x1)) -> l(a(x1)) r(a(a(x1))) -> a(a(r(x1))) b(l(x1)) -> b(a(r(x1))) r(b(x1)) -> l(b(x1)) The certificate found is represented by the following graph. The certificate consists of the following enumerated nodes: 1, 3, 8, 10, 11, 16, 17, 18, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30 Node 1 is start node and node 3 is final node. Those nodes are connected through the following edges: * 1 to 8 labelled l_1(0)* 1 to 10 labelled a_1(0), b_1(0)* 1 to 22 labelled l_1(1)* 1 to 23 labelled b_1(1)* 3 to 3 labelled #_1(0)* 8 to 3 labelled a_1(0), b_1(0)* 8 to 16 labelled l_1(1)* 8 to 17 labelled b_1(1)* 8 to 26 labelled b_1(2)* 10 to 11 labelled a_1(0)* 10 to 21 labelled l_1(1)* 11 to 3 labelled r_1(0)* 11 to 17 labelled a_1(1)* 11 to 20 labelled l_1(1)* 11 to 28 labelled l_1(2)* 16 to 3 labelled a_1(1)* 16 to 16 labelled l_1(1)* 17 to 18 labelled a_1(1)* 17 to 25 labelled l_1(2)* 18 to 3 labelled r_1(1)* 18 to 17 labelled a_1(1)* 18 to 20 labelled l_1(1)* 18 to 28 labelled l_1(2)* 20 to 3 labelled b_1(1)* 20 to 17 labelled b_1(1)* 20 to 26 labelled b_1(2)* 21 to 20 labelled a_1(1)* 21 to 28 labelled a_1(1)* 22 to 21 labelled a_1(1)* 23 to 24 labelled a_1(1)* 24 to 21 labelled r_1(1)* 24 to 26 labelled a_1(2)* 25 to 20 labelled a_1(2)* 25 to 28 labelled a_1(2)* 26 to 27 labelled a_1(2)* 27 to 25 labelled r_1(2)* 27 to 29 labelled a_1(3)* 28 to 25 labelled a_1(2)* 29 to 30 labelled a_1(3)* 30 to 25 labelled r_1(3)* 30 to 29 labelled a_1(3) ---------------------------------------- (2) YES popout

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