details

property	value
status	complete
benchmark	bag-sum-prod.xml
ran by	Akihisa Yamada
cpu timeout	1200 seconds
wallclock timeout	300 seconds
memory limit	137438953472 bytes
execution host	n151.star.cs.uiowa.edu
space	Mixed_AC

run statistics

property	value
solver	AProVE
configuration	standard
runtime (wallclock)	1.59744 seconds
cpu usage	3.38836
user time	3.25152
system time	0.136846
max virtual memory	1.8275312E7
max residence set size	215184.0

stage attributes

key	value
starexec-result	YES

output

YES proof of /export/starexec/sandbox/benchmark/theBenchmark.xml # AProVE Commit ID: 794c25de1cacf0d048858bcd21c9a779e1221865 marcel 20200619 unpublished dirty Termination of the given ETRS could be proven: (0) ETRS (1) EDirectTerminationProof [EQUIVALENT, 0 ms] (2) YES ---------------------------------------- (0) Obligation: Equational rewrite system: The TRS R consists of the following rules: +(0, x) -> x +(s(x), s(y)) -> s(s(+(x, y))) *(0, x) -> 0 *(s(x), s(y)) -> s(+(+(x, y), *(x, y))) U(empty, b) -> b sum(empty) -> 0 sum(singl(x)) -> x sum(U(x, y)) -> +(sum(x), sum(y)) prod(empty) -> s(0) prod(singl(x)) -> x prod(U(x, y)) -> *(prod(x), prod(y)) The set E consists of the following equations: *(x, y) == *(y, x) +(x, y) == +(y, x) U(x, y) == U(y, x) *(*(x, y), z) == *(x, *(y, z)) +(+(x, y), z) == +(x, +(y, z)) U(U(x, y), z) == U(x, U(y, z)) ---------------------------------------- (1) EDirectTerminationProof (EQUIVALENT) We use [DA_FALKE] with the following order to prove termination. Precedence: U_2 > +_2 > s_1 U_2 > sum_1 empty > 0 prod_1 > *_2 > +_2 > s_1 Status: *_2: flat status +_2: flat status U_2: flat status ---------------------------------------- (2) YES popout

output may be truncated. 'popout' for the full output.

job log

popout

actions

all output return to TRS Equational