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TRS Innermost pair #487093067
details
property
value
status
complete
benchmark
Ex2_Luc03b_L.xml
ran by
Akihisa Yamada
cpu timeout
1200 seconds
wallclock timeout
300 seconds
memory limit
137438953472 bytes
execution host
n144.star.cs.uiowa.edu
space
Transformed_CSR_innermost_04
run statistics
property
value
solver
AProVE
configuration
standard
runtime (wallclock)
1.67075 seconds
cpu usage
3.5712
user time
3.42354
system time
0.147656
max virtual memory
1.8408912E7
max residence set size
229656.0
stage attributes
key
value
starexec-result
YES
output
YES proof of /export/starexec/sandbox2/benchmark/theBenchmark.xml # AProVE Commit ID: 794c25de1cacf0d048858bcd21c9a779e1221865 marcel 20200619 unpublished dirty Termination w.r.t. Q of the given QTRS could be proven: (0) QTRS (1) QTRSRRRProof [EQUIVALENT, 31 ms] (2) QTRS (3) RisEmptyProof [EQUIVALENT, 0 ms] (4) YES ---------------------------------------- (0) Obligation: Q restricted rewrite system: The TRS R consists of the following rules: fst(0, Z) -> nil fst(s, cons(Y)) -> cons(Y) from(X) -> cons(X) add(0, X) -> X add(s, Y) -> s len(nil) -> 0 len(cons(X)) -> s The set Q consists of the following terms: fst(0, x0) fst(s, cons(x0)) from(x0) add(0, x0) add(s, x0) len(nil) len(cons(x0)) ---------------------------------------- (1) QTRSRRRProof (EQUIVALENT) Used ordering: Knuth-Bendix order [KBO] with precedence:nil > len_1 > s > add_2 > from_1 > cons_1 > 0 > fst_2 and weight map: 0=2 nil=1 s=3 cons_1=1 from_1=2 len_1=1 fst_2=0 add_2=0 The variable weight is 1With this ordering the following rules can be removed by the rule removal processor [LPAR04] because they are oriented strictly: fst(0, Z) -> nil fst(s, cons(Y)) -> cons(Y) from(X) -> cons(X) add(0, X) -> X add(s, Y) -> s len(nil) -> 0 len(cons(X)) -> s ---------------------------------------- (2) Obligation: Q restricted rewrite system: R is empty. The set Q consists of the following terms: fst(0, x0) fst(s, cons(x0)) from(x0) add(0, x0) add(s, x0) len(nil) len(cons(x0)) ---------------------------------------- (3) RisEmptyProof (EQUIVALENT) The TRS R is empty. Hence, termination is trivially proven. ---------------------------------------- (4) YES
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