details

property	value
status	complete
benchmark	PEANO_nosorts_noand_GM.xml
ran by	Akihisa Yamada
cpu timeout	1200 seconds
wallclock timeout	300 seconds
memory limit	137438953472 bytes
execution host	n146.star.cs.uiowa.edu
space	Transformed_CSR_innermost_04

run statistics

property	value
solver	muterm 6.0.3
configuration	default
runtime (wallclock)	0.217527 seconds
cpu usage	0.229772
user time	0.164288
system time	0.065484
max virtual memory	113188.0
max residence set size	6836.0

stage attributes

key	value
starexec-result	YES

output

YES Problem 1: (VAR v_NonEmpty:S M:S N:S X:S X1:S X2:S X3:S) (RULES a__U11(tt,M:S,N:S) -> a__U12(tt,M:S,N:S) a__U11(X1:S,X2:S,X3:S) -> U11(X1:S,X2:S,X3:S) a__U12(tt,M:S,N:S) -> s(a__plus(mark(N:S),mark(M:S))) a__U12(X1:S,X2:S,X3:S) -> U12(X1:S,X2:S,X3:S) a__plus(N:S,0) -> mark(N:S) a__plus(N:S,s(M:S)) -> a__U11(tt,M:S,N:S) a__plus(X1:S,X2:S) -> plus(X1:S,X2:S) mark(0) -> 0 mark(U11(X1:S,X2:S,X3:S)) -> a__U11(mark(X1:S),X2:S,X3:S) mark(U12(X1:S,X2:S,X3:S)) -> a__U12(mark(X1:S),X2:S,X3:S) mark(plus(X1:S,X2:S)) -> a__plus(mark(X1:S),mark(X2:S)) mark(s(X:S)) -> s(mark(X:S)) mark(tt) -> tt ) (STRATEGY INNERMOST) Problem 1: Dependency Pairs Processor: -> Pairs: A__U11(tt,M:S,N:S) -> A__U12(tt,M:S,N:S) A__U12(tt,M:S,N:S) -> A__PLUS(mark(N:S),mark(M:S)) A__U12(tt,M:S,N:S) -> MARK(M:S) A__U12(tt,M:S,N:S) -> MARK(N:S) A__PLUS(N:S,0) -> MARK(N:S) A__PLUS(N:S,s(M:S)) -> A__U11(tt,M:S,N:S) MARK(U11(X1:S,X2:S,X3:S)) -> A__U11(mark(X1:S),X2:S,X3:S) MARK(U11(X1:S,X2:S,X3:S)) -> MARK(X1:S) MARK(U12(X1:S,X2:S,X3:S)) -> A__U12(mark(X1:S),X2:S,X3:S) MARK(U12(X1:S,X2:S,X3:S)) -> MARK(X1:S) MARK(plus(X1:S,X2:S)) -> A__PLUS(mark(X1:S),mark(X2:S)) MARK(plus(X1:S,X2:S)) -> MARK(X1:S) MARK(plus(X1:S,X2:S)) -> MARK(X2:S) MARK(s(X:S)) -> MARK(X:S) -> Rules: a__U11(tt,M:S,N:S) -> a__U12(tt,M:S,N:S) a__U11(X1:S,X2:S,X3:S) -> U11(X1:S,X2:S,X3:S) a__U12(tt,M:S,N:S) -> s(a__plus(mark(N:S),mark(M:S))) a__U12(X1:S,X2:S,X3:S) -> U12(X1:S,X2:S,X3:S) a__plus(N:S,0) -> mark(N:S) a__plus(N:S,s(M:S)) -> a__U11(tt,M:S,N:S) a__plus(X1:S,X2:S) -> plus(X1:S,X2:S) mark(0) -> 0 mark(U11(X1:S,X2:S,X3:S)) -> a__U11(mark(X1:S),X2:S,X3:S) mark(U12(X1:S,X2:S,X3:S)) -> a__U12(mark(X1:S),X2:S,X3:S) mark(plus(X1:S,X2:S)) -> a__plus(mark(X1:S),mark(X2:S)) mark(s(X:S)) -> s(mark(X:S)) mark(tt) -> tt Problem 1: SCC Processor: -> Pairs: A__U11(tt,M:S,N:S) -> A__U12(tt,M:S,N:S) A__U12(tt,M:S,N:S) -> A__PLUS(mark(N:S),mark(M:S)) A__U12(tt,M:S,N:S) -> MARK(M:S) A__U12(tt,M:S,N:S) -> MARK(N:S) A__PLUS(N:S,0) -> MARK(N:S) A__PLUS(N:S,s(M:S)) -> A__U11(tt,M:S,N:S) MARK(U11(X1:S,X2:S,X3:S)) -> A__U11(mark(X1:S),X2:S,X3:S) MARK(U11(X1:S,X2:S,X3:S)) -> MARK(X1:S) MARK(U12(X1:S,X2:S,X3:S)) -> A__U12(mark(X1:S),X2:S,X3:S) MARK(U12(X1:S,X2:S,X3:S)) -> MARK(X1:S) MARK(plus(X1:S,X2:S)) -> A__PLUS(mark(X1:S),mark(X2:S)) MARK(plus(X1:S,X2:S)) -> MARK(X1:S) MARK(plus(X1:S,X2:S)) -> MARK(X2:S) MARK(s(X:S)) -> MARK(X:S) -> Rules: a__U11(tt,M:S,N:S) -> a__U12(tt,M:S,N:S) a__U11(X1:S,X2:S,X3:S) -> U11(X1:S,X2:S,X3:S) a__U12(tt,M:S,N:S) -> s(a__plus(mark(N:S),mark(M:S))) a__U12(X1:S,X2:S,X3:S) -> U12(X1:S,X2:S,X3:S) a__plus(N:S,0) -> mark(N:S) a__plus(N:S,s(M:S)) -> a__U11(tt,M:S,N:S) a__plus(X1:S,X2:S) -> plus(X1:S,X2:S) mark(0) -> 0 mark(U11(X1:S,X2:S,X3:S)) -> a__U11(mark(X1:S),X2:S,X3:S) mark(U12(X1:S,X2:S,X3:S)) -> a__U12(mark(X1:S),X2:S,X3:S) mark(plus(X1:S,X2:S)) -> a__plus(mark(X1:S),mark(X2:S)) mark(s(X:S)) -> s(mark(X:S)) mark(tt) -> tt ->Strongly Connected Components: ->->Cycle: ->->-> Pairs: A__U11(tt,M:S,N:S) -> A__U12(tt,M:S,N:S) A__U12(tt,M:S,N:S) -> A__PLUS(mark(N:S),mark(M:S)) A__U12(tt,M:S,N:S) -> MARK(M:S) A__U12(tt,M:S,N:S) -> MARK(N:S) A__PLUS(N:S,0) -> MARK(N:S) A__PLUS(N:S,s(M:S)) -> A__U11(tt,M:S,N:S) MARK(U11(X1:S,X2:S,X3:S)) -> A__U11(mark(X1:S),X2:S,X3:S) MARK(U11(X1:S,X2:S,X3:S)) -> MARK(X1:S) MARK(U12(X1:S,X2:S,X3:S)) -> A__U12(mark(X1:S),X2:S,X3:S) MARK(U12(X1:S,X2:S,X3:S)) -> MARK(X1:S) popout

output may be truncated. 'popout' for the full output.

job log

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actions

all output return to TRS Innermost