details

property	value
status	complete
benchmark	h41.xml
ran by	Akihisa Yamada
cpu timeout	1200 seconds
wallclock timeout	300 seconds
memory limit	137438953472 bytes
execution host	n150.star.cs.uiowa.edu
space	Hamana_Kikuchi_18

run statistics

property	value
solver	Wanda 2.2a
configuration	default
runtime (wallclock)	18.1808 seconds
cpu usage	19.1541
user time	17.8086
system time	1.34554
max virtual memory	934308.0
max residence set size	145232.0

stage attributes

key	value
starexec-result	YES

output

YES We consider the system theBenchmark. Alphabet: 0 : [] --> A active : [] --> A -> A afterNth : [] --> A -> A -> A app : [] --> (A -> A) -> A -> A cons : [] --> A -> A -> A fst : [] --> A -> A head : [] --> A -> A map : [] --> (A -> A) -> A -> A mark : [] --> A -> A natsFrom : [] --> A -> A nil : [] --> A pair : [] --> A -> A -> A s : [] --> A -> A sel : [] --> A -> A -> A snd : [] --> A -> A splitAt : [] --> A -> A -> A tail : [] --> A -> A take : [] --> A -> A -> A tt : [] --> A u11 : [] --> A -> A -> A -> A u12 : [] --> A -> A -> A -> A u21 : [] --> A -> A -> A u22 : [] --> A -> A -> A u31 : [] --> A -> A -> A u32 : [] --> A -> A -> A u41 : [] --> A -> A -> A -> A u42 : [] --> A -> A -> A -> A u51 : [] --> A -> A -> A u52 : [] --> A -> A -> A u61 : [] --> A -> A -> A -> A -> A u62 : [] --> A -> A -> A -> A -> A u63 : [] --> A -> A -> A -> A -> A u64 : [] --> A -> A -> A u71 : [] --> A -> A -> A u72 : [] --> A -> A -> A u81 : [] --> A -> A -> A -> A u82 : [] --> A -> A -> A -> A Rules: active (u11 tt x y) => mark (u12 tt x y) active (u12 tt x y) => mark (snd (splitAt x y)) active (u21 tt x) => mark (u22 tt x) active (u22 tt x) => mark x active (u31 tt x) => mark (u32 tt x) active (u32 tt x) => mark x active (u41 tt x y) => mark (u42 tt x y) active (u42 tt x y) => mark (head (afterNth x y)) active (u51 tt x) => mark (u52 tt x) active (u52 tt x) => mark x active (u61 tt x y z) => mark (u62 tt x y z) active (u62 tt x y z) => mark (u63 tt x y z) active (u63 tt x y z) => mark (u64 (splitAt x z) y) active (u64 (pair x y) z) => mark (pair (cons z x) y) active (u71 tt x) => mark (u72 tt x) active (u72 tt x) => mark x active (u81 tt x y) => mark (u82 tt x y) active (u82 tt x y) => mark (fst (splitAt x y)) active (afterNth x y) => mark (u11 tt x y) active (fst (pair x y)) => mark (u21 tt x) active (head (cons x y)) => mark (u31 tt x) active (natsFrom x) => mark (cons x (natsFrom (s x))) active (sel x y) => mark (u41 tt x y) active (snd (pair x y)) => mark (u51 tt y) active (splitAt 0 x) => mark (pair nil x) active (splitAt (s x) (cons y z)) => mark (u61 tt x y z) active (tail (cons x y)) => mark (u71 tt y) active (take x y) => mark (u81 tt x y) mark (u11 x y z) => active (u11 (mark x) y z) mark tt => active tt mark (u12 x y z) => active (u12 (mark x) y z) mark (snd x) => active (snd (mark x)) mark (splitAt x y) => active (splitAt (mark x) (mark y)) mark (u21 x y) => active (u21 (mark x) y) mark (u22 x y) => active (u22 (mark x) y) mark (u31 x y) => active (u31 (mark x) y) mark (u32 x y) => active (u32 (mark x) y) mark (u41 x y z) => active (u41 (mark x) y z) mark (u42 x y z) => active (u42 (mark x) y z) mark (head x) => active (head (mark x)) mark (afterNth x y) => active (afterNth (mark x) (mark y)) mark (u51 x y) => active (u51 (mark x) y) mark (u52 x y) => active (u52 (mark x) y) mark (u61 x y z u) => active (u61 (mark x) y z u) mark (u62 x y z u) => active (u62 (mark x) y z u) mark (u63 x y z u) => active (u63 (mark x) y z u) mark (u64 x y) => active (u64 (mark x) y) mark (pair x y) => active (pair (mark x) (mark y)) mark (cons x y) => active (cons (mark x) y) mark (u71 x y) => active (u71 (mark x) y) mark (u72 x y) => active (u72 (mark x) y) mark (u81 x y z) => active (u81 (mark x) y z) mark (u82 x y z) => active (u82 (mark x) y z) mark (fst x) => active (fst (mark x)) mark (natsFrom x) => active (natsFrom (mark x)) popout

output may be truncated. 'popout' for the full output.

job log

popout

actions

all output return to Higher Order Rewriting Union Beta