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SRS Standard pair #487510696
details
property
value
status
complete
benchmark
random-319.xml
ran by
Akihisa Yamada
cpu timeout
1200 seconds
wallclock timeout
300 seconds
memory limit
137438953472 bytes
execution host
n090.star.cs.uiowa.edu
space
Waldmann_19
run statistics
property
value
solver
matchbox-2020-06-25
configuration
tc20-std.sh
runtime (wallclock)
4.54039406776 seconds
cpu usage
17.720488302
max memory
6.23730688E8
stage attributes
key
value
output-size
6624
starexec-result
YES
output
/export/starexec/sandbox/solver/bin/starexec_run_tc20-std.sh /export/starexec/sandbox/benchmark/theBenchmark.xml /export/starexec/sandbox/output/output_files -------------------------------------------------------------------------------- YES ************************************************** summary ************************************************** SRS with 3 rules on 2 letters mirror SRS with 3 rules on 2 letters DP SRS with 10 strict rules and 3 weak rules on 4 letters weights SRS with 2 strict rules and 3 weak rules on 3 letters EDG SRS with 2 strict rules and 3 weak rules on 3 letters Matrix { monotone = Weak, domain = Arctic, shape = Full, bits = 4, dim = 3, solver = Minisatapi, verbose = False, tracing = False} SRS with 1 strict rules and 3 weak rules on 3 letters EDG SRS with 1 strict rules and 3 weak rules on 3 letters Matrix { monotone = Weak, domain = Arctic, shape = Full, bits = 4, dim = 2, solver = Minisatapi, verbose = False, tracing = False} SRS with 0 strict rules and 3 weak rules on 2 letters EDG ************************************************** proof ************************************************** property Termination has value Just True for SRS [a, b, a, b] -> [b, b, b, b] {- Input 0 -} [a, a, b, b] -> [a, a, a, b] {- Input 1 -} [b, a, b, a] -> [a, b, a, b] {- Input 2 -} reason mirror property Termination has value Just True for SRS [b, a, b, a] -> [b, b, b, b] {- Mirror (Input 0) -} [b, b, a, a] -> [b, a, a, a] {- Mirror (Input 1) -} [a, b, a, b] -> [b, a, b, a] {- Mirror (Input 2) -} reason DP property Termination has value Just True for SRS [b, a, b, a] ->= [b, b, b, b] {- DP Nontop (Mirror (Input 0)) -} [b, b, a, a] ->= [b, a, a, a] {- DP Nontop (Mirror (Input 1)) -} [a, b, a, b] ->= [b, a, b, a] {- DP Nontop (Mirror (Input 2)) -} [a#, b, a, b] |-> [a#] {- DP (Top 3) (Mirror (Input 2)) -} [a#, b, a, b] |-> [a#, b, a] {- DP (Top 1) (Mirror (Input 2)) -} [a#, b, a, b] |-> [b#, a] {- DP (Top 2) (Mirror (Input 2)) -} [a#, b, a, b] |-> [b#, a, b, a] {- DP (Top 0) (Mirror (Input 2)) -} [b#, a, b, a] |-> [b#] {- DP (Top 3) (Mirror (Input 0)) -} [b#, a, b, a] |-> [b#, b] {- DP (Top 2) (Mirror (Input 0)) -} [b#, a, b, a] |-> [b#, b, b] {- DP (Top 1) (Mirror (Input 0)) -} [b#, a, b, a] |-> [b#, b, b, b] {- DP (Top 0) (Mirror (Input 0)) -} [b#, b, a, a] |-> [a#, a, a] {- DP (Top 1) (Mirror (Input 1)) -} [b#, b, a, a] |-> [b#, a, a, a] {- DP (Top 0) (Mirror (Input 1)) -} reason (b, 2/1) (a, 2/1) (a#, 1/1) property Termination has value Just True for SRS [b, a, b, a] ->= [b, b, b, b] {- DP Nontop (Mirror (Input 0)) -} [b, b, a, a] ->= [b, a, a, a] {- DP Nontop (Mirror (Input 1)) -} [a, b, a, b] ->= [b, a, b, a] {- DP Nontop (Mirror (Input 2)) -} [b#, a, b, a] |-> [b#, b, b, b] {- DP (Top 0) (Mirror (Input 0)) -} [b#, b, a, a] |-> [b#, a, a, a] {- DP (Top 0) (Mirror (Input 1)) -} reason EDG property Termination has value Just True for SRS [b#, a, b, a] |-> [b#, b, b, b] {- DP (Top 0) (Mirror (Input 0)) -} [b#, b, a, a] |-> [b#, a, a, a] {- DP (Top 0) (Mirror (Input 1)) -} [b, a, b, a] ->= [b, b, b, b] {- DP Nontop (Mirror (Input 0)) -} [b, b, a, a] ->= [b, a, a, a] {- DP Nontop (Mirror (Input 1)) -} [a, b, a, b] ->= [b, a, b, a] {- DP Nontop (Mirror (Input 2)) -} reason ( b , Wk / 3A 3A 3A \ | 3A 3A 3A | \ 0A 3A 3A / ) ( a , Wk / 3A 3A 6A \ | 0A 3A 3A | \ 0A 3A 3A / ) ( b# , Wk / 28A 31A 31A \ | 28A 31A 31A | \ 28A 31A 31A / ) property Termination has value Just True for SRS [b#, a, b, a] |-> [b#, b, b, b] {- DP (Top 0) (Mirror (Input 0)) -} [b, a, b, a] ->= [b, b, b, b] {- DP Nontop (Mirror (Input 0)) -} [b, b, a, a] ->= [b, a, a, a] {- DP Nontop (Mirror (Input 1)) -} [a, b, a, b] ->= [b, a, b, a] {- DP Nontop (Mirror (Input 2)) -} reason EDG property Termination has value Just True
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