details

property	value
status	complete
benchmark	random-78.xml
ran by	Akihisa Yamada
cpu timeout	1200 seconds
wallclock timeout	300 seconds
memory limit	137438953472 bytes
execution host	n129.star.cs.uiowa.edu
space	Waldmann_19

run statistics

property	value
solver	matchbox-2020-06-25
configuration	tc20-std.sh
runtime (wallclock)	166.85868907 seconds
cpu usage	665.44831855
max memory	4.775256064E9

stage attributes

key	value
output-size	8337
starexec-result	YES

output

/export/starexec/sandbox2/solver/bin/starexec_run_tc20-std.sh /export/starexec/sandbox2/benchmark/theBenchmark.xml /export/starexec/sandbox2/output/output_files -------------------------------------------------------------------------------- YES ************************************************** summary ************************************************** SRS with 3 rules on 2 letters mirror SRS with 3 rules on 2 letters DP SRS with 12 strict rules and 3 weak rules on 4 letters weights SRS with 3 strict rules and 3 weak rules on 4 letters EDG 2 sub-proofs 1 SRS with 1 strict rules and 3 weak rules on 3 letters Matrix { monotone = Weak, domain = Arctic, shape = Full, bits = 4, dim = 5, solver = Minisatapi, verbose = False, tracing = False} SRS with 0 strict rules and 3 weak rules on 2 letters EDG 2 SRS with 2 strict rules and 3 weak rules on 3 letters Matrix { monotone = Weak, domain = Arctic, shape = Full, bits = 4, dim = 2, solver = Minisatapi, verbose = False, tracing = False} SRS with 1 strict rules and 3 weak rules on 3 letters EDG SRS with 1 strict rules and 3 weak rules on 3 letters Matrix { monotone = Weak, domain = Arctic, shape = Full, bits = 3, dim = 4, solver = Minisatapi, verbose = False, tracing = False} SRS with 0 strict rules and 3 weak rules on 2 letters EDG ************************************************** proof ************************************************** property Termination has value Just True for SRS [a, b, a, b] -> [b, b, a, b] {- Input 0 -} [b, b, a, a] -> [a, b, a, a] {- Input 1 -} [a, a, b, b] -> [b, a, a, b] {- Input 2 -} reason mirror property Termination has value Just True for SRS [b, a, b, a] -> [b, a, b, b] {- Mirror (Input 0) -} [a, a, b, b] -> [a, a, b, a] {- Mirror (Input 1) -} [b, b, a, a] -> [b, a, a, b] {- Mirror (Input 2) -} reason DP property Termination has value Just True for SRS [b, a, b, a] ->= [b, a, b, b] {- DP Nontop (Mirror (Input 0)) -} [a, a, b, b] ->= [a, a, b, a] {- DP Nontop (Mirror (Input 1)) -} [b, b, a, a] ->= [b, a, a, b] {- DP Nontop (Mirror (Input 2)) -} [a#, a, b, b] |-> [a#] {- DP (Top 3) (Mirror (Input 1)) -} [a#, a, b, b] |-> [a#, a, b, a] {- DP (Top 0) (Mirror (Input 1)) -} [a#, a, b, b] |-> [a#, b, a] {- DP (Top 1) (Mirror (Input 1)) -} [a#, a, b, b] |-> [b#, a] {- DP (Top 2) (Mirror (Input 1)) -} [b#, a, b, a] |-> [a#, b, b] {- DP (Top 1) (Mirror (Input 0)) -} [b#, a, b, a] |-> [b#] {- DP (Top 3) (Mirror (Input 0)) -} [b#, a, b, a] |-> [b#, a, b, b] {- DP (Top 0) (Mirror (Input 0)) -} [b#, a, b, a] |-> [b#, b] {- DP (Top 2) (Mirror (Input 0)) -} [b#, b, a, a] |-> [a#, a, b] {- DP (Top 1) (Mirror (Input 2)) -} [b#, b, a, a] |-> [a#, b] {- DP (Top 2) (Mirror (Input 2)) -} [b#, b, a, a] |-> [b#] {- DP (Top 3) (Mirror (Input 2)) -} [b#, b, a, a] |-> [b#, a, a, b] {- DP (Top 0) (Mirror (Input 2)) -} reason (b, 1/18) (a, 1/18) property Termination has value Just True for SRS [b, a, b, a] ->= [b, a, b, b] {- DP Nontop (Mirror (Input 0)) -} [a, a, b, b] ->= [a, a, b, a] {- DP Nontop (Mirror (Input 1)) -} [b, b, a, a] ->= [b, a, a, b] {- DP Nontop (Mirror (Input 2)) -} [a#, a, b, b] |-> [a#, a, b, a] {- DP (Top 0) (Mirror (Input 1)) -} [b#, a, b, a] |-> [b#, a, b, b] {- DP (Top 0) (Mirror (Input 0)) -} [b#, b, a, a] |-> [b#, a, a, b] {- DP (Top 0) (Mirror (Input 2)) -} reason EDG property Termination has value Just True for SRS [a#, a, b, b] |-> [a#, a, b, a] {- DP (Top 0) (Mirror (Input 1)) -} [b, a, b, a] ->= [b, a, b, b] {- DP Nontop (Mirror (Input 0)) -} [a, a, b, b] ->= [a, a, b, a] {- DP Nontop (Mirror (Input 1)) -} [b, b, a, a] ->= [b, a, a, b] {- DP Nontop (Mirror (Input 2)) -} reason ( b , Wk / 15A 15A 20A 20A 20A \ | 15A 15A 15A 15A 15A | | 10A 10A 15A 15A 15A | | 10A 10A 15A 15A 15A | \ 10A 10A 15A 15A 15A / ) ( a , Wk / 10A 10A 15A 15A 15A \ | 10A 10A 15A 15A 15A | | 10A 10A 15A 15A 15A | | 10A 10A 10A 15A 15A | \ 5A 10A 10A 10A 10A / ) ( a# , Wk / 13A 13A 13A 13A 18A \ | 13A 13A 13A 13A 18A | | 13A 13A 13A 13A 18A | | 13A 13A 13A 13A 18A | \ 13A 13A 13A 13A 18A / ) popout

output may be truncated. 'popout' for the full output.

job log

popout

actions

all output return to SRS Standard