details

property	value
status	complete
benchmark	random-266.xml
ran by	Akihisa Yamada
cpu timeout	1200 seconds
wallclock timeout	300 seconds
memory limit	137438953472 bytes
execution host	n108.star.cs.uiowa.edu
space	Waldmann_19

run statistics

property	value
solver	matchbox-2020-06-25
configuration	tc20-std.sh
runtime (wallclock)	1.97115898132 seconds
cpu usage	7.51327382
max memory	3.56102144E8

stage attributes

key	value
output-size	7132
starexec-result	YES

output

/export/starexec/sandbox2/solver/bin/starexec_run_tc20-std.sh /export/starexec/sandbox2/benchmark/theBenchmark.xml /export/starexec/sandbox2/output/output_files -------------------------------------------------------------------------------- YES ************************************************** summary ************************************************** SRS with 3 rules on 2 letters mirror SRS with 3 rules on 2 letters DP SRS with 7 strict rules and 3 weak rules on 4 letters weights SRS with 3 strict rules and 3 weak rules on 4 letters EDG SRS with 3 strict rules and 3 weak rules on 4 letters Matrix { monotone = Weak, domain = Arctic, shape = Full, bits = 4, dim = 2, solver = Minisatapi, verbose = False, tracing = False} SRS with 2 strict rules and 3 weak rules on 4 letters EDG SRS with 2 strict rules and 3 weak rules on 4 letters Matrix { monotone = Weak, domain = Arctic, shape = Full, bits = 4, dim = 2, solver = Minisatapi, verbose = False, tracing = False} SRS with 1 strict rules and 3 weak rules on 4 letters weights SRS with 0 strict rules and 3 weak rules on 2 letters EDG ************************************************** proof ************************************************** property Termination has value Just True for SRS [b, a, a, b] -> [b, a, a, a] {- Input 0 -} [a, b, b, a] -> [a, a, b, b] {- Input 1 -} [b, a, a, a] -> [b, b, b, a] {- Input 2 -} reason mirror property Termination has value Just True for SRS [b, a, a, b] -> [a, a, a, b] {- Mirror (Input 0) -} [a, b, b, a] -> [b, b, a, a] {- Mirror (Input 1) -} [a, a, a, b] -> [a, b, b, b] {- Mirror (Input 2) -} reason DP property Termination has value Just True for SRS [b, a, a, b] ->= [a, a, a, b] {- DP Nontop (Mirror (Input 0)) -} [a, b, b, a] ->= [b, b, a, a] {- DP Nontop (Mirror (Input 1)) -} [a, a, a, b] ->= [a, b, b, b] {- DP Nontop (Mirror (Input 2)) -} [b#, a, a, b] |-> [a#, a, a, b] {- DP (Top 0) (Mirror (Input 0)) -} [a#, b, b, a] |-> [b#, b, a, a] {- DP (Top 0) (Mirror (Input 1)) -} [a#, b, b, a] |-> [b#, a, a] {- DP (Top 1) (Mirror (Input 1)) -} [a#, b, b, a] |-> [a#, a] {- DP (Top 2) (Mirror (Input 1)) -} [a#, a, a, b] |-> [b#, b] {- DP (Top 2) (Mirror (Input 2)) -} [a#, a, a, b] |-> [b#, b, b] {- DP (Top 1) (Mirror (Input 2)) -} [a#, a, a, b] |-> [a#, b, b, b] {- DP (Top 0) (Mirror (Input 2)) -} reason (b, 1/6) (a, 1/6) property Termination has value Just True for SRS [b, a, a, b] ->= [a, a, a, b] {- DP Nontop (Mirror (Input 0)) -} [a, b, b, a] ->= [b, b, a, a] {- DP Nontop (Mirror (Input 1)) -} [a, a, a, b] ->= [a, b, b, b] {- DP Nontop (Mirror (Input 2)) -} [b#, a, a, b] |-> [a#, a, a, b] {- DP (Top 0) (Mirror (Input 0)) -} [a#, b, b, a] |-> [b#, b, a, a] {- DP (Top 0) (Mirror (Input 1)) -} [a#, a, a, b] |-> [a#, b, b, b] {- DP (Top 0) (Mirror (Input 2)) -} reason EDG property Termination has value Just True for SRS [b#, a, a, b] |-> [a#, a, a, b] {- DP (Top 0) (Mirror (Input 0)) -} [a#, a, a, b] |-> [a#, b, b, b] {- DP (Top 0) (Mirror (Input 2)) -} [a#, b, b, a] |-> [b#, b, a, a] {- DP (Top 0) (Mirror (Input 1)) -} [b, a, a, b] ->= [a, a, a, b] {- DP Nontop (Mirror (Input 0)) -} [a, b, b, a] ->= [b, b, a, a] {- DP Nontop (Mirror (Input 1)) -} [a, a, a, b] ->= [a, b, b, b] {- DP Nontop (Mirror (Input 2)) -} reason ( b , Wk / 2A 2A \ \ 2A 2A / ) ( a , Wk / 2A 4A \ \ 0A 2A / ) ( b# , Wk / 21A 22A \ \ 21A 22A / ) ( a# , Wk / 21A 22A \ \ 21A 22A / ) property Termination has value Just True for SRS [b#, a, a, b] |-> [a#, a, a, b] {- DP (Top 0) (Mirror (Input 0)) -} [a#, b, b, a] |-> [b#, b, a, a] {- DP (Top 0) (Mirror (Input 1)) -} [b, a, a, b] ->= [a, a, a, b] {- DP Nontop (Mirror (Input 0)) -} [a, b, b, a] ->= [b, b, a, a] {- DP Nontop (Mirror (Input 1)) -} [a, a, a, b] ->= [a, b, b, b] {- DP Nontop (Mirror (Input 2)) -} reason EDG property Termination has value Just True popout

output may be truncated. 'popout' for the full output.

job log

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actions

all output return to SRS Standard