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SRS Standard pair #487511238
details
property
value
status
complete
benchmark
loop1.xml
ran by
Akihisa Yamada
cpu timeout
1200 seconds
wallclock timeout
300 seconds
memory limit
137438953472 bytes
execution host
n077.star.cs.uiowa.edu
space
Zantema_06
run statistics
property
value
solver
MultumNonMulta 3.16 29 June 2020 60G
configuration
default
runtime (wallclock)
0.451442956924 seconds
cpu usage
0.663073475
max memory
3.44768512E8
stage attributes
key
value
output-size
749
starexec-result
NO
output
/export/starexec/sandbox2/solver/bin/starexec_run_default /export/starexec/sandbox2/benchmark/theBenchmark.xml /export/starexec/sandbox2/output/output_files -------------------------------------------------------------------------------- NO After renaming modulo { a->0, b->1 }, it remains to prove termination of the 2-rule system { 0 1 1 -> 1 1 0 0 , 0 0 -> 1 } Loop of length 6 starting with a string of length 7 using right expansion and the encoding { 0->a, 1->b, ... }: .abb.bbbb rule abb-> bbaa at position 0 .bbaa.bbbb rule abb-> bbaa at position 3 .bbabbaa.bb rule abb-> bbaa at position 6 .bbabbabbaa. rule abb-> bbaa at position 5 .bbabbbbaaaa. rule aa-> b at position 7 .bbabbbbbaa. rule aa-> b at position 8 .bbabbbbbb.
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