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SRS Standard pair #487511662
details
property
value
status
complete
benchmark
07.xml
ran by
Akihisa Yamada
cpu timeout
1200 seconds
wallclock timeout
300 seconds
memory limit
137438953472 bytes
execution host
n185.star.cs.uiowa.edu
space
Mixed_SRS
run statistics
property
value
solver
matchbox-2020-06-25
configuration
tc20-std.sh
runtime (wallclock)
79.7383611202 seconds
cpu usage
315.559293917
max memory
6.851395584E9
stage attributes
key
value
output-size
9352
starexec-result
YES
output
/export/starexec/sandbox/solver/bin/starexec_run_tc20-std.sh /export/starexec/sandbox/benchmark/theBenchmark.xml /export/starexec/sandbox/output/output_files -------------------------------------------------------------------------------- YES ************************************************** summary ************************************************** SRS with 2 rules on 2 letters mirror SRS with 2 rules on 2 letters DP SRS with 6 strict rules and 2 weak rules on 4 letters EDG SRS with 6 strict rules and 2 weak rules on 4 letters Matrix { monotone = Weak, domain = Arctic, shape = Full, bits = 4, dim = 3, solver = Minisatapi, verbose = False, tracing = False} SRS with 5 strict rules and 2 weak rules on 4 letters EDG SRS with 5 strict rules and 2 weak rules on 4 letters Matrix { monotone = Weak, domain = Arctic, shape = Full, bits = 4, dim = 3, solver = Minisatapi, verbose = False, tracing = False} SRS with 4 strict rules and 2 weak rules on 4 letters EDG SRS with 4 strict rules and 2 weak rules on 4 letters Matrix { monotone = Weak, domain = Arctic, shape = Full, bits = 4, dim = 3, solver = Minisatapi, verbose = False, tracing = False} SRS with 3 strict rules and 2 weak rules on 4 letters EDG SRS with 3 strict rules and 2 weak rules on 4 letters Matrix { monotone = Weak, domain = Arctic, shape = Full, bits = 4, dim = 3, solver = Minisatapi, verbose = False, tracing = False} SRS with 2 strict rules and 2 weak rules on 4 letters weights SRS with 0 strict rules and 2 weak rules on 2 letters EDG ************************************************** proof ************************************************** property Termination has value Just True for SRS [a, a, b, b] -> [a, b, a, a] {- Input 0 -} [a] -> [b, b, b] {- Input 1 -} reason mirror property Termination has value Just True for SRS [b, b, a, a] -> [a, a, b, a] {- Mirror (Input 0) -} [a] -> [b, b, b] {- Mirror (Input 1) -} reason DP property Termination has value Just True for SRS [b, b, a, a] ->= [a, a, b, a] {- DP Nontop (Mirror (Input 0)) -} [a] ->= [b, b, b] {- DP Nontop (Mirror (Input 1)) -} [a#] |-> [b#] {- DP (Top 2) (Mirror (Input 1)) -} [a#] |-> [b#, b] {- DP (Top 1) (Mirror (Input 1)) -} [a#] |-> [b#, b, b] {- DP (Top 0) (Mirror (Input 1)) -} [b#, b, a, a] |-> [a#, a, b, a] {- DP (Top 0) (Mirror (Input 0)) -} [b#, b, a, a] |-> [a#, b, a] {- DP (Top 1) (Mirror (Input 0)) -} [b#, b, a, a] |-> [b#, a] {- DP (Top 2) (Mirror (Input 0)) -} reason EDG property Termination has value Just True for SRS [a#] |-> [b#] {- DP (Top 2) (Mirror (Input 1)) -} [b#, b, a, a] |-> [b#, a] {- DP (Top 2) (Mirror (Input 0)) -} [b#, b, a, a] |-> [a#, b, a] {- DP (Top 1) (Mirror (Input 0)) -} [a#] |-> [b#, b, b] {- DP (Top 0) (Mirror (Input 1)) -} [b#, b, a, a] |-> [a#, a, b, a] {- DP (Top 0) (Mirror (Input 0)) -} [a#] |-> [b#, b] {- DP (Top 1) (Mirror (Input 1)) -} [b, b, a, a] ->= [a, a, b, a] {- DP Nontop (Mirror (Input 0)) -} [a] ->= [b, b, b] {- DP Nontop (Mirror (Input 1)) -} reason ( b , Wk / - 0A 0A \ | 0A - 0A | \ - - 0A / ) ( a , Wk / - 0A 0A \ | 0A 2A 2A | \ - - 0A / ) ( a# , Wk / 11A 13A 14A \ | 3A 1A 5A | \ - - 0A / ) ( b# , Wk / 11A 11A 14A \ | 1A - - | \ - - 0A / ) property Termination has value Just True for SRS [a#] |-> [b#] {- DP (Top 2) (Mirror (Input 1)) -} [b#, b, a, a] |-> [a#, b, a] {- DP (Top 1) (Mirror (Input 0)) -} [a#] |-> [b#, b, b] {- DP (Top 0) (Mirror (Input 1)) -} [b#, b, a, a] |-> [a#, a, b, a] {- DP (Top 0) (Mirror (Input 0)) -} [a#] |-> [b#, b] {- DP (Top 1) (Mirror (Input 1)) -} [b, b, a, a] ->= [a, a, b, a] {- DP Nontop (Mirror (Input 0)) -} [a] ->= [b, b, b] {- DP Nontop (Mirror (Input 1)) -} reason EDG property Termination has value Just True for SRS [a#] |-> [b#] {- DP (Top 2) (Mirror (Input 1)) -} [b#, b, a, a] |-> [a#, a, b, a] {- DP (Top 0) (Mirror (Input 0)) -} [a#] |-> [b#, b] {- DP (Top 1) (Mirror (Input 1)) -} [b#, b, a, a] |-> [a#, b, a] {- DP (Top 1) (Mirror (Input 0)) -}
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