details

property	value
status	complete
benchmark	05.xml
ran by	Akihisa Yamada
cpu timeout	1200 seconds
wallclock timeout	300 seconds
memory limit	137438953472 bytes
execution host	n190.star.cs.uiowa.edu
space	Mixed_SRS

run statistics

property	value
solver	matchbox-2020-06-25
configuration	tc20-std.sh
runtime (wallclock)	12.1233551502 seconds
cpu usage	47.365740864
max memory	1.61542144E9

stage attributes

key	value
output-size	8061
starexec-result	YES

output

/export/starexec/sandbox2/solver/bin/starexec_run_tc20-std.sh /export/starexec/sandbox2/benchmark/theBenchmark.xml /export/starexec/sandbox2/output/output_files -------------------------------------------------------------------------------- YES ************************************************** summary ************************************************** SRS with 2 rules on 2 letters DP SRS with 8 strict rules and 2 weak rules on 4 letters EDG SRS with 8 strict rules and 2 weak rules on 4 letters Matrix { monotone = Weak, domain = Arctic, shape = Full, bits = 4, dim = 2, solver = Minisatapi, verbose = False, tracing = False} SRS with 7 strict rules and 2 weak rules on 4 letters EDG SRS with 7 strict rules and 2 weak rules on 4 letters Matrix { monotone = Weak, domain = Arctic, shape = Full, bits = 4, dim = 2, solver = Minisatapi, verbose = False, tracing = False} SRS with 6 strict rules and 2 weak rules on 4 letters EDG SRS with 6 strict rules and 2 weak rules on 4 letters Matrix { monotone = Weak, domain = Arctic, shape = Full, bits = 4, dim = 3, solver = Minisatapi, verbose = False, tracing = False} SRS with 3 strict rules and 2 weak rules on 4 letters weights SRS with 0 strict rules and 2 weak rules on 2 letters EDG ************************************************** proof ************************************************** property Termination has value Just True for SRS [a, a, b, a] -> [a, b, b, b] {- Input 0 -} [b, b, b] -> [b, a, a, a] {- Input 1 -} reason DP property Termination has value Just True for SRS [a, a, b, a] ->= [a, b, b, b] {- DP Nontop (Input 0) -} [b, b, b] ->= [b, a, a, a] {- DP Nontop (Input 1) -} [a#, a, b, a] |-> [a#, b, b, b] {- DP (Top 0) (Input 0) -} [a#, a, b, a] |-> [b#] {- DP (Top 3) (Input 0) -} [a#, a, b, a] |-> [b#, b] {- DP (Top 2) (Input 0) -} [a#, a, b, a] |-> [b#, b, b] {- DP (Top 1) (Input 0) -} [b#, b, b] |-> [a#] {- DP (Top 3) (Input 1) -} [b#, b, b] |-> [a#, a] {- DP (Top 2) (Input 1) -} [b#, b, b] |-> [a#, a, a] {- DP (Top 1) (Input 1) -} [b#, b, b] |-> [b#, a, a, a] {- DP (Top 0) (Input 1) -} reason EDG property Termination has value Just True for SRS [a#, a, b, a] |-> [a#, b, b, b] {- DP (Top 0) (Input 0) -} [a#, a, b, a] |-> [b#, b, b] {- DP (Top 1) (Input 0) -} [b#, b, b] |-> [b#, a, a, a] {- DP (Top 0) (Input 1) -} [b#, b, b] |-> [a#, a, a] {- DP (Top 1) (Input 1) -} [a#, a, b, a] |-> [b#, b] {- DP (Top 2) (Input 0) -} [b#, b, b] |-> [a#, a] {- DP (Top 2) (Input 1) -} [a#, a, b, a] |-> [b#] {- DP (Top 3) (Input 0) -} [b#, b, b] |-> [a#] {- DP (Top 3) (Input 1) -} [a, a, b, a] ->= [a, b, b, b] {- DP Nontop (Input 0) -} [b, b, b] ->= [b, a, a, a] {- DP Nontop (Input 1) -} reason ( a , Wk / 0A 0A \ \ 0A 0A / ) ( b , Wk / 0A 0A \ \ -2A -2A / ) ( a# , Wk / 9A 11A \ \ 9A 11A / ) ( b# , Wk / 11A 11A \ \ 11A 11A / ) property Termination has value Just True for SRS [a#, a, b, a] |-> [b#, b, b] {- DP (Top 1) (Input 0) -} [b#, b, b] |-> [b#, a, a, a] {- DP (Top 0) (Input 1) -} [b#, b, b] |-> [a#, a, a] {- DP (Top 1) (Input 1) -} [a#, a, b, a] |-> [b#, b] {- DP (Top 2) (Input 0) -} [b#, b, b] |-> [a#, a] {- DP (Top 2) (Input 1) -} [a#, a, b, a] |-> [b#] {- DP (Top 3) (Input 0) -} [b#, b, b] |-> [a#] {- DP (Top 3) (Input 1) -} [a, a, b, a] ->= [a, b, b, b] {- DP Nontop (Input 0) -} [b, b, b] ->= [b, a, a, a] {- DP Nontop (Input 1) -} reason EDG property Termination has value Just True for SRS [a#, a, b, a] |-> [b#, b, b] {- DP (Top 1) (Input 0) -} [b#, b, b] |-> [a#] {- DP (Top 3) (Input 1) -} [a#, a, b, a] |-> [b#] {- DP (Top 3) (Input 0) -} [b#, b, b] |-> [a#, a] {- DP (Top 2) (Input 1) -} [a#, a, b, a] |-> [b#, b] {- DP (Top 2) (Input 0) -} [b#, b, b] |-> [a#, a, a] {- DP (Top 1) (Input 1) -} [b#, b, b] |-> [b#, a, a, a] {- DP (Top 0) (Input 1) -} [a, a, b, a] ->= [a, b, b, b] {- DP Nontop (Input 0) -} [b, b, b] ->= [b, a, a, a] {- DP Nontop (Input 1) -} reason ( a , Wk / 0A 0A \ popout

output may be truncated. 'popout' for the full output.

job log

popout

actions

all output return to SRS Standard