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SRS Standard pair #487511982
details
property
value
status
complete
benchmark
size-12-alpha-3-num-135.xml
ran by
Akihisa Yamada
cpu timeout
1200 seconds
wallclock timeout
300 seconds
memory limit
137438953472 bytes
execution host
n173.star.cs.uiowa.edu
space
Waldmann_07_size12
run statistics
property
value
solver
MultumNonMulta 3.16 29 June 2020 60G
configuration
default
runtime (wallclock)
1.46312093735 seconds
cpu usage
2.551803596
max memory
5.60381952E8
stage attributes
key
value
output-size
1091
starexec-result
NO
output
/export/starexec/sandbox/solver/bin/starexec_run_default /export/starexec/sandbox/benchmark/theBenchmark.xml /export/starexec/sandbox/output/output_files -------------------------------------------------------------------------------- NO After renaming modulo { a->0, b->1, c->2 }, it remains to prove termination of the 4-rule system { 0 -> , 0 1 -> , 1 1 -> 2 , 2 0 -> 0 0 1 2 } Loop of length 14 starting with a string of length 7 using right expansion and the encoding { 0->a, 1->b, ... }: .bb.aaaaa rule bb-> c at position 0 .c.aaaaa rule ca-> aabc at position 0 .aabc.aaaa rule ca-> aabc at position 3 .aabaabc.aaa rule a-> at position 3 .aababc.aaa rule a-> at position 3 .aabbc.aaa rule ca-> aabc at position 4 .aabbaabc.aa rule ca-> aabc at position 7 .aabbaabaabc.a rule a-> at position 7 .aabbaababc.a rule a-> at position 7 .aabbaabbc.a rule bb-> c at position 6 .aabbaacc.a rule ca-> aabc at position 7 .aabbaacaabc. rule ca-> aabc at position 6 .aabbaaaabcabc. rule ab-> at position 7 .aabbaaacabc. rule ca-> aabc at position 7 .aabbaaaaabcbc.
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