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SRS Standard pair #487512168
details
property
value
status
complete
benchmark
size-12-alpha-3-num-23.xml
ran by
Akihisa Yamada
cpu timeout
1200 seconds
wallclock timeout
300 seconds
memory limit
137438953472 bytes
execution host
n136.star.cs.uiowa.edu
space
Waldmann_07_size12
run statistics
property
value
solver
MultumNonMulta 3.16 29 June 2020 60G
configuration
default
runtime (wallclock)
0.623322963715 seconds
cpu usage
1.132299014
max memory
3.94850304E8
stage attributes
key
value
output-size
911
starexec-result
NO
output
/export/starexec/sandbox/solver/bin/starexec_run_default /export/starexec/sandbox/benchmark/theBenchmark.xml /export/starexec/sandbox/output/output_files -------------------------------------------------------------------------------- NO After renaming modulo { a->0, b->1, c->2 }, it remains to prove termination of the 4-rule system { 0 -> , 0 -> 1 , 1 1 2 -> 2 2 0 0 0 , 2 -> } Loop of length 10 starting with a string of length 6 using right expansion and the encoding { 0->a, 1->b, ... }: .a.bcbcc rule a-> b at position 0 .b.bcbcc rule bbc-> ccaaa at position 0 .ccaaa.bcc rule a-> b at position 3 .ccaba.bcc rule a-> b at position 4 .ccabb.bcc rule bbc-> ccaaa at position 4 .ccabccaaa.c rule c-> at position 4 .ccabcaaa.c rule a-> b at position 5 .ccabcbaa.c rule a-> b at position 6 .ccabcbba.c rule a-> b at position 7 .ccabcbbb.c rule bbc-> ccaaa at position 6 .ccabcbccaaa.
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