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SRS Standard pair #487512492
details
property
value
status
complete
benchmark
size-12-alpha-3-num-101.xml
ran by
Akihisa Yamada
cpu timeout
1200 seconds
wallclock timeout
300 seconds
memory limit
137438953472 bytes
execution host
n079.star.cs.uiowa.edu
space
Waldmann_07_size12
run statistics
property
value
solver
MultumNonMulta 3.16 29 June 2020 60G
configuration
default
runtime (wallclock)
0.783401012421 seconds
cpu usage
1.620688085
max memory
4.37129216E8
stage attributes
key
value
output-size
1038
starexec-result
NO
output
/export/starexec/sandbox/solver/bin/starexec_run_default /export/starexec/sandbox/benchmark/theBenchmark.xml /export/starexec/sandbox/output/output_files -------------------------------------------------------------------------------- NO After renaming modulo { a->0, b->1, c->2 }, it remains to prove termination of the 4-rule system { 0 -> , 0 0 0 -> 1 , 1 2 -> 2 2 0 1 , 2 -> } Loop of length 13 starting with a string of length 7 using right expansion and the encoding { 0->a, 1->b, ... }: .bc.ccccc rule bc-> ccab at position 0 .ccab.ccccc rule bc-> ccab at position 3 .ccaccab.cccc rule c-> at position 3 .ccacab.cccc rule c-> at position 3 .ccaab.cccc rule bc-> ccab at position 4 .ccaaccab.ccc rule c-> at position 4 .ccaacab.ccc rule c-> at position 4 .ccaaab.ccc rule aaa-> b at position 2 .ccbb.ccc rule bc-> ccab at position 3 .ccbccab.cc rule a-> at position 5 .ccbccb.cc rule bc-> ccab at position 5 .ccbccccab.c rule a-> at position 7 .ccbccccb.c rule bc-> ccab at position 7 .ccbccccccab.
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