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SRS Standard pair #487512834
details
property
value
status
complete
benchmark
size-12-alpha-3-num-181.xml
ran by
Akihisa Yamada
cpu timeout
1200 seconds
wallclock timeout
300 seconds
memory limit
137438953472 bytes
execution host
n125.star.cs.uiowa.edu
space
Waldmann_07_size12
run statistics
property
value
solver
MultumNonMulta 3.16 29 June 2020 60G
configuration
default
runtime (wallclock)
0.451123952866 seconds
cpu usage
0.730672948
max memory
3.44424448E8
stage attributes
key
value
output-size
918
starexec-result
NO
output
/export/starexec/sandbox/solver/bin/starexec_run_default /export/starexec/sandbox/benchmark/theBenchmark.xml /export/starexec/sandbox/output/output_files -------------------------------------------------------------------------------- NO After renaming modulo { a->0, b->1, c->2 }, it remains to prove termination of the 4-rule system { 0 -> , 0 1 -> 1 0 2 1 2 , 1 -> 0 , 2 2 -> } Loop of length 11 starting with a string of length 4 using right expansion and the encoding { 0->a, 1->b, ... }: .ab.cb rule ab-> bacbc at position 0 .bacbc.cb rule b-> a at position 0 .aacbc.cb rule b-> a at position 3 .aacac.cb rule cc-> at position 4 .aaca.b rule ab-> bacbc at position 3 .aacbacbc. rule b-> a at position 3 .aacaacbc. rule a-> at position 3 .aacacbc. rule a-> at position 3 .aaccbc. rule cc-> at position 2 .aabc. rule ab-> bacbc at position 1 .abacbcc. rule a-> at position 2 .abcbcc.
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