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SRS Standard pair #487512868
details
property
value
status
complete
benchmark
size-12-alpha-3-num-86.xml
ran by
Akihisa Yamada
cpu timeout
1200 seconds
wallclock timeout
300 seconds
memory limit
137438953472 bytes
execution host
n090.star.cs.uiowa.edu
space
Waldmann_07_size12
run statistics
property
value
solver
matchbox-2020-06-25
configuration
tc20-std.sh
runtime (wallclock)
35.680109024 seconds
cpu usage
141.867761945
max memory
2.58084864E9
stage attributes
key
value
output-size
9255
starexec-result
YES
output
/export/starexec/sandbox/solver/bin/starexec_run_tc20-std.sh /export/starexec/sandbox/benchmark/theBenchmark.xml /export/starexec/sandbox/output/output_files -------------------------------------------------------------------------------- YES ************************************************** summary ************************************************** SRS with 4 rules on 3 letters mirror SRS with 4 rules on 3 letters DP SRS with 6 strict rules and 4 weak rules on 6 letters EDG SRS with 6 strict rules and 4 weak rules on 6 letters Matrix { monotone = Weak, domain = Arctic, shape = Full, bits = 4, dim = 3, solver = Minisatapi, verbose = False, tracing = False} SRS with 5 strict rules and 4 weak rules on 6 letters EDG SRS with 5 strict rules and 4 weak rules on 6 letters Matrix { monotone = Weak, domain = Arctic, shape = Full, bits = 4, dim = 3, solver = Minisatapi, verbose = False, tracing = False} SRS with 4 strict rules and 4 weak rules on 6 letters EDG SRS with 4 strict rules and 4 weak rules on 6 letters Matrix { monotone = Weak, domain = Arctic, shape = Full, bits = 4, dim = 3, solver = Minisatapi, verbose = False, tracing = False} SRS with 3 strict rules and 4 weak rules on 6 letters weights SRS with 0 strict rules and 4 weak rules on 3 letters EDG ************************************************** proof ************************************************** property Termination has value Just True for SRS [a] -> [] {- Input 0 -} [a, a] -> [b, a, c, b] {- Input 1 -} [b] -> [c] {- Input 2 -} [b, c] -> [a] {- Input 3 -} reason mirror property Termination has value Just True for SRS [a] -> [] {- Mirror (Input 0) -} [a, a] -> [b, c, a, b] {- Mirror (Input 1) -} [b] -> [c] {- Mirror (Input 2) -} [c, b] -> [a] {- Mirror (Input 3) -} reason DP property Termination has value Just True for SRS [a] ->= [] {- DP Nontop (Mirror (Input 0)) -} [a, a] ->= [b, c, a, b] {- DP Nontop (Mirror (Input 1)) -} [b] ->= [c] {- DP Nontop (Mirror (Input 2)) -} [c, b] ->= [a] {- DP Nontop (Mirror (Input 3)) -} [a#, a] |-> [a#, b] {- DP (Top 2) (Mirror (Input 1)) -} [a#, a] |-> [b#] {- DP (Top 3) (Mirror (Input 1)) -} [a#, a] |-> [b#, c, a, b] {- DP (Top 0) (Mirror (Input 1)) -} [a#, a] |-> [c#, a, b] {- DP (Top 1) (Mirror (Input 1)) -} [b#] |-> [c#] {- DP (Top 0) (Mirror (Input 2)) -} [c#, b] |-> [a#] {- DP (Top 0) (Mirror (Input 3)) -} reason EDG property Termination has value Just True for SRS [a#, a] |-> [a#, b] {- DP (Top 2) (Mirror (Input 1)) -} [a#, a] |-> [c#, a, b] {- DP (Top 1) (Mirror (Input 1)) -} [c#, b] |-> [a#] {- DP (Top 0) (Mirror (Input 3)) -} [a#, a] |-> [b#, c, a, b] {- DP (Top 0) (Mirror (Input 1)) -} [b#] |-> [c#] {- DP (Top 0) (Mirror (Input 2)) -} [a#, a] |-> [b#] {- DP (Top 3) (Mirror (Input 1)) -} [a] ->= [] {- DP Nontop (Mirror (Input 0)) -} [a, a] ->= [b, c, a, b] {- DP Nontop (Mirror (Input 1)) -} [b] ->= [c] {- DP Nontop (Mirror (Input 2)) -} [c, b] ->= [a] {- DP Nontop (Mirror (Input 3)) -} reason ( a , Wk / 2A 4A 2A \ | 0A 0A 0A | \ - - 0A / ) ( b , Wk / 0A 2A 0A \ | 0A 2A 0A | \ - - 0A / ) ( c , Wk / - 2A 0A \ | - 0A - | \ - - 0A / ) ( a# , Wk / 6A 8A 1A \ | 7A 5A 9A | \ - - 0A / ) ( b# , Wk / 5A 6A 7A \ | 5A 9A 6A | \ - - 0A / ) ( c# , Wk / 4A 6A - \ | 4A 9A 6A | \ - - 0A / ) property Termination has value Just True for SRS [a#, a] |-> [a#, b] {- DP (Top 2) (Mirror (Input 1)) -} [a#, a] |-> [c#, a, b] {- DP (Top 1) (Mirror (Input 1)) -}
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