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SRS Standard pair #487513302
details
property
value
status
complete
benchmark
size-12-alpha-3-num-179.xml
ran by
Akihisa Yamada
cpu timeout
1200 seconds
wallclock timeout
300 seconds
memory limit
137438953472 bytes
execution host
n075.star.cs.uiowa.edu
space
Waldmann_07_size12
run statistics
property
value
solver
MultumNonMulta 3.16 29 June 2020 60G
configuration
default
runtime (wallclock)
0.501336097717 seconds
cpu usage
0.66597468
max memory
3.44113152E8
stage attributes
key
value
output-size
958
starexec-result
NO
output
/export/starexec/sandbox/solver/bin/starexec_run_default /export/starexec/sandbox/benchmark/theBenchmark.xml /export/starexec/sandbox/output/output_files -------------------------------------------------------------------------------- NO After renaming modulo { a->0, b->1, c->2 }, it remains to prove termination of the 3-rule system { 0 -> , 0 1 -> 1 0 2 1 0 0 , 2 1 2 -> } The system was reversed. After renaming modulo { 0->0, 1->1, 2->2 }, it remains to prove termination of the 3-rule system { 0 -> , 1 0 -> 0 0 1 2 0 1 , 2 1 2 -> } Loop of length 7 starting with a string of length 4 using right expansion and the encoding { 0->a, 1->b, ... }: .ba.aa rule ba-> aabcab at position 0 .aabcab.aa rule a-> at position 4 .aabcb.aa rule ba-> aabcab at position 4 .aabcaabcab.a rule a-> at position 4 .aabcabcab.a rule a-> at position 4 .aabcbcab.a rule cbc-> at position 3 .aabab.a rule ba-> aabcab at position 4 .aabaaabcab.
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