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SRS Standard pair #487513332
details
property
value
status
complete
benchmark
size-12-alpha-3-num-177.xml
ran by
Akihisa Yamada
cpu timeout
1200 seconds
wallclock timeout
300 seconds
memory limit
137438953472 bytes
execution host
n108.star.cs.uiowa.edu
space
Waldmann_07_size12
run statistics
property
value
solver
MultumNonMulta 3.16 29 June 2020 60G
configuration
default
runtime (wallclock)
0.511368989944 seconds
cpu usage
0.754923109
max memory
3.52423936E8
stage attributes
key
value
output-size
977
starexec-result
NO
output
/export/starexec/sandbox/solver/bin/starexec_run_default /export/starexec/sandbox/benchmark/theBenchmark.xml /export/starexec/sandbox/output/output_files -------------------------------------------------------------------------------- NO After renaming modulo { a->0, b->1, c->2 }, it remains to prove termination of the 4-rule system { 0 -> , 0 1 -> 1 0 2 1 0 , 1 -> 0 , 2 2 -> } The system was reversed. After renaming modulo { 0->0, 1->1, 2->2 }, it remains to prove termination of the 4-rule system { 0 -> , 1 0 -> 0 1 2 0 1 , 1 -> 0 , 2 2 -> } Loop of length 8 starting with a string of length 3 using right expansion and the encoding { 0->a, 1->b, ... }: .ba.a rule ba-> abcab at position 0 .abcab.a rule a-> at position 3 .abcb.a rule ba-> abcab at position 3 .abcabcab. rule a-> at position 3 .abcbcab. rule b-> a at position 3 .abcacab. rule a-> at position 3 .abccab. rule cc-> at position 2 .abab. rule b-> a at position 3 .abaa.
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