Spaces
Explore
Communities
Statistics
Reports
Cluster
Status
Help
SRS Standard pair #487514292
details
property
value
status
complete
benchmark
4819.xml
ran by
Akihisa Yamada
cpu timeout
1200 seconds
wallclock timeout
300 seconds
memory limit
137438953472 bytes
execution host
n072.star.cs.uiowa.edu
space
ICFP_2010
run statistics
property
value
solver
MultumNonMulta 3.16 29 June 2020 60G
configuration
default
runtime (wallclock)
5.64492797852 seconds
cpu usage
20.92338934
max memory
3.719335936E9
stage attributes
key
value
output-size
426762
starexec-result
YES
output
/export/starexec/sandbox2/solver/bin/starexec_run_default /export/starexec/sandbox2/benchmark/theBenchmark.xml /export/starexec/sandbox2/output/output_files -------------------------------------------------------------------------------- YES After renaming modulo { 0->0, 1->1, 2->2, 3->3, 5->4, 4->5 }, it remains to prove termination of the 52-rule system { 0 1 2 3 -> 0 0 2 2 0 1 0 4 4 5 , 0 1 5 0 -> 1 4 5 2 2 5 2 2 5 2 , 1 2 4 2 -> 1 3 5 5 1 5 1 0 1 0 , 2 1 2 0 -> 0 2 0 0 5 2 2 0 5 2 , 3 2 4 3 -> 3 2 3 3 2 0 1 0 0 2 , 3 3 4 0 -> 3 0 1 4 5 3 1 3 0 2 , 5 1 5 2 -> 5 2 2 2 2 2 1 0 3 2 , 0 5 4 1 2 -> 0 5 0 3 0 5 4 1 4 4 , 1 2 3 5 0 -> 1 5 5 0 3 2 0 2 1 0 , 1 2 4 2 4 -> 1 3 2 3 0 0 4 0 3 0 , 2 1 2 4 2 -> 0 2 3 2 2 0 0 4 3 2 , 2 2 4 5 4 -> 2 0 2 0 3 4 4 1 4 4 , 2 4 3 1 2 -> 3 5 5 0 5 5 2 5 3 0 , 2 4 4 4 0 -> 3 2 2 2 4 4 5 1 0 0 , 3 2 1 5 2 -> 0 5 3 1 1 4 4 0 2 2 , 3 3 3 4 0 -> 3 2 5 1 4 0 0 0 0 0 , 5 3 3 1 5 -> 5 1 0 0 2 2 5 3 3 0 , 4 3 1 2 5 -> 4 4 5 1 3 0 0 3 0 5 , 0 1 5 0 1 5 -> 0 2 0 1 3 5 3 1 4 2 , 0 3 1 2 4 3 -> 0 1 0 5 4 4 5 1 4 3 , 0 3 2 1 5 2 -> 0 1 0 0 2 0 3 4 3 2 , 1 2 4 1 5 3 -> 0 3 3 5 3 0 1 0 3 3 , 2 4 4 3 2 4 -> 0 0 0 3 0 2 1 5 2 3 , 2 4 4 3 4 3 -> 3 2 2 1 4 3 0 2 0 3 , 3 2 1 2 1 2 -> 3 3 4 1 1 3 1 0 2 2 , 3 3 4 0 5 2 -> 3 0 0 2 0 5 1 5 5 2 , 3 5 0 0 4 1 -> 3 0 0 5 2 1 0 3 0 1 , 3 4 3 3 1 2 -> 1 4 5 3 3 4 5 4 2 2 , 5 1 5 3 1 3 -> 5 0 2 2 2 3 2 5 5 3 , 5 3 4 5 4 2 -> 4 3 0 3 2 2 3 1 4 2 , 4 1 0 1 2 0 -> 4 5 2 1 0 2 5 3 1 0 , 4 2 4 4 2 1 -> 1 4 5 4 3 2 3 2 0 1 , 4 3 1 3 4 2 -> 4 0 1 0 2 0 0 0 4 2 , 4 3 4 5 4 3 -> 4 3 0 0 0 5 1 0 5 5 , 4 4 3 0 4 3 -> 4 5 3 0 5 2 2 5 3 0 , 1 1 5 1 2 1 5 -> 1 2 4 2 0 0 3 1 4 4 , 1 2 0 4 4 3 5 -> 0 4 5 5 1 4 0 5 5 5 , 1 3 1 2 4 4 3 -> 3 3 3 0 5 5 0 0 3 3 , 1 3 3 1 2 1 2 -> 3 1 3 3 0 1 3 5 4 4 , 1 5 1 2 3 5 4 -> 1 1 0 5 5 2 4 5 5 4 , 2 0 4 5 4 3 4 -> 2 0 2 1 5 5 0 0 0 5 , 2 5 4 0 4 2 4 -> 0 5 3 2 1 1 1 5 2 3 , 2 4 1 2 5 0 4 -> 0 0 4 4 4 0 0 0 3 3 , 3 1 2 4 3 3 3 -> 1 0 3 0 4 1 1 4 4 0 , 3 1 5 3 4 3 4 -> 0 0 0 3 5 2 5 1 2 4 , 3 1 4 2 4 1 0 -> 3 5 5 2 3 5 0 5 0 2 , 5 1 5 3 3 4 3 -> 5 2 1 3 0 5 3 2 2 0 , 5 3 5 2 4 4 1 -> 4 2 0 5 1 3 0 1 1 1 , 5 4 0 5 5 4 3 -> 5 5 4 1 1 1 4 5 5 0 , 5 4 3 1 1 2 5 -> 5 5 1 5 5 3 2 1 0 5 , 4 1 1 5 4 0 4 -> 4 0 3 5 2 1 1 4 4 3 , 4 2 5 1 2 4 0 -> 4 5 3 0 0 5 5 1 4 0 } Applying sparse tiling TRFC(2) [Geser/Hofbauer/Waldmann, FSCD 2019]. After renaming modulo { (0,0)->0, (0,1)->1, (1,2)->2, (2,3)->3, (3,0)->4, (0,2)->5, (2,2)->6, (2,0)->7, (1,0)->8, (0,4)->9, (4,4)->10, (4,5)->11, (5,0)->12, (3,1)->13, (5,1)->14, (3,2)->15, (5,2)->16, (3,3)->17, (5,3)->18, (3,4)->19, (5,4)->20, (3,5)->21, (5,5)->22, (3,7)->23, (5,7)->24, (4,0)->25, (6,0)->26, (1,5)->27, (1,4)->28, (2,5)->29, (2,1)->30, (0,3)->31, (2,4)->32, (0,5)->33, (0,7)->34, (2,7)->35, (1,1)->36, (4,1)->37, (6,1)->38, (4,2)->39, (1,3)->40, (6,2)->41, (4,3)->42, (6,3)->43, (6,5)->44, (4,7)->45, (6,4)->46, (1,7)->47 }, it remains to prove termination of the 2548-rule system { 0 1 2 3 4 -> 0 0 5 6 7 1 8 9 10 11 12 , 0 1 2 3 13 -> 0 0 5 6 7 1 8 9 10 11 14 , 0 1 2 3 15 -> 0 0 5 6 7 1 8 9 10 11 16 , 0 1 2 3 17 -> 0 0 5 6 7 1 8 9 10 11 18 , 0 1 2 3 19 -> 0 0 5 6 7 1 8 9 10 11 20 , 0 1 2 3 21 -> 0 0 5 6 7 1 8 9 10 11 22 , 0 1 2 3 23 -> 0 0 5 6 7 1 8 9 10 11 24 , 8 1 2 3 4 -> 8 0 5 6 7 1 8 9 10 11 12 , 8 1 2 3 13 -> 8 0 5 6 7 1 8 9 10 11 14 , 8 1 2 3 15 -> 8 0 5 6 7 1 8 9 10 11 16 , 8 1 2 3 17 -> 8 0 5 6 7 1 8 9 10 11 18 , 8 1 2 3 19 -> 8 0 5 6 7 1 8 9 10 11 20 , 8 1 2 3 21 -> 8 0 5 6 7 1 8 9 10 11 22 , 8 1 2 3 23 -> 8 0 5 6 7 1 8 9 10 11 24 , 7 1 2 3 4 -> 7 0 5 6 7 1 8 9 10 11 12 , 7 1 2 3 13 -> 7 0 5 6 7 1 8 9 10 11 14 , 7 1 2 3 15 -> 7 0 5 6 7 1 8 9 10 11 16 , 7 1 2 3 17 -> 7 0 5 6 7 1 8 9 10 11 18 , 7 1 2 3 19 -> 7 0 5 6 7 1 8 9 10 11 20 , 7 1 2 3 21 -> 7 0 5 6 7 1 8 9 10 11 22 , 7 1 2 3 23 -> 7 0 5 6 7 1 8 9 10 11 24 , 4 1 2 3 4 -> 4 0 5 6 7 1 8 9 10 11 12 , 4 1 2 3 13 -> 4 0 5 6 7 1 8 9 10 11 14 , 4 1 2 3 15 -> 4 0 5 6 7 1 8 9 10 11 16 , 4 1 2 3 17 -> 4 0 5 6 7 1 8 9 10 11 18 , 4 1 2 3 19 -> 4 0 5 6 7 1 8 9 10 11 20 , 4 1 2 3 21 -> 4 0 5 6 7 1 8 9 10 11 22 , 4 1 2 3 23 -> 4 0 5 6 7 1 8 9 10 11 24 , 25 1 2 3 4 -> 25 0 5 6 7 1 8 9 10 11 12 , 25 1 2 3 13 -> 25 0 5 6 7 1 8 9 10 11 14 , 25 1 2 3 15 -> 25 0 5 6 7 1 8 9 10 11 16 , 25 1 2 3 17 -> 25 0 5 6 7 1 8 9 10 11 18 ,
popout
output may be truncated. 'popout' for the full output.
job log
popout
actions
all output
return to SRS Standard