SRS Standard pair #487515018

details
property	value
status	complete
benchmark	88208.xml
ran by	Akihisa Yamada
cpu timeout	1200 seconds
wallclock timeout	300 seconds
memory limit	137438953472 bytes
execution host	n116.star.cs.uiowa.edu
space	ICFP_2010
run statistics
property	value
solver	MultumNonMulta 3.16 29 June 2020 60G
configuration	default
runtime (wallclock)	2.03648686409 seconds
cpu usage	6.336448314
max memory	1.604186112E9
stage attributes
key	value
output-size	215294
starexec-result	YES
output
/export/starexec/sandbox2/solver/bin/starexec_run_default /export/starexec/sandbox2/benchmark/theBenchmark.xml /export/starexec/sandbox2/output/output_files


--------------------------------------------------------------------------------


YES

After renaming modulo { 0->0, 1->1, 2->2, 3->3 }, 
it remains to prove termination of the 30-rule system
{ 0 0 0 1 0 2 2 3 3 2 3 3 0 -> 3 3 1 1 3 3 3 1 3 1 3 2 1 0 3 3 1 ,
  0 0 2 2 1 0 2 3 1 3 1 1 0 -> 1 0 1 0 2 1 3 3 3 3 2 3 2 3 1 1 0 ,
  0 1 1 0 2 1 0 1 3 0 1 3 3 -> 0 3 3 3 0 2 3 3 0 3 3 2 1 3 3 1 3 ,
  0 1 1 1 3 3 0 3 2 3 3 1 2 -> 3 3 1 1 0 2 1 2 3 0 3 3 3 2 3 0 2 ,
  0 1 1 3 0 1 1 1 1 3 1 3 1 -> 2 3 1 1 0 3 3 1 3 2 1 3 3 1 2 1 3 ,
  0 1 2 3 2 2 2 1 2 3 0 0 0 -> 1 1 3 3 0 3 3 1 2 3 1 3 3 0 0 1 1 ,
  0 2 3 0 0 0 0 2 3 1 0 3 1 -> 1 1 2 2 1 2 3 0 2 1 3 1 2 3 3 2 1 ,
  0 2 3 3 0 0 2 2 3 0 3 1 3 -> 3 1 3 3 2 1 0 0 1 0 3 3 3 1 3 2 1 ,
  0 3 3 0 3 0 3 0 3 3 3 0 0 -> 1 1 0 3 3 1 1 2 3 2 3 3 3 0 2 1 1 ,
  1 0 1 3 2 2 2 1 2 1 3 3 2 -> 3 3 1 0 0 2 3 3 3 2 3 1 3 1 3 1 1 ,
  1 1 0 3 2 0 1 0 3 3 2 0 2 -> 1 3 0 0 3 2 1 1 2 3 3 2 1 1 1 1 2 ,
  1 2 0 1 0 3 1 3 0 2 1 2 3 -> 1 3 1 3 1 0 1 0 0 3 3 3 1 3 2 3 3 ,
  1 2 1 0 1 1 2 3 2 1 1 0 0 -> 3 1 3 3 3 3 3 1 1 2 3 2 1 0 1 0 1 ,
  1 2 2 1 1 2 0 3 3 3 0 3 2 -> 1 3 1 3 3 3 3 1 3 2 1 3 3 2 2 3 2 ,
  1 2 2 3 3 3 3 3 0 0 3 2 2 -> 1 3 3 3 3 1 1 2 3 1 1 3 1 0 0 1 0 ,
  2 0 1 1 2 1 0 3 2 1 3 1 3 -> 0 3 3 0 2 2 1 3 1 2 3 1 3 1 3 3 3 ,
  2 0 2 0 2 1 3 0 0 0 2 3 0 -> 2 3 1 2 3 3 2 2 0 3 1 1 3 3 3 2 0 ,
  2 0 2 2 1 3 1 3 0 1 3 2 1 -> 2 0 1 3 3 1 3 3 2 3 0 2 1 1 0 2 1 ,
  2 1 3 0 2 3 2 2 1 2 3 2 3 -> 2 1 1 1 2 1 2 1 3 1 3 1 1 0 3 3 3 ,
  2 3 1 0 3 3 3 0 0 3 0 0 3 -> 1 1 2 2 3 3 3 3 1 3 3 1 2 3 3 3 1 ,
  3 0 1 2 2 0 3 1 0 1 2 0 1 -> 3 3 2 2 3 1 0 2 3 3 1 2 1 0 1 1 1 ,
  3 0 2 2 1 0 0 3 1 2 1 1 1 -> 3 2 3 1 3 1 2 3 1 0 0 2 3 1 2 3 1 ,
  3 0 2 2 1 3 3 1 1 0 1 0 2 -> 3 2 1 1 1 3 3 1 3 1 3 1 1 2 1 3 3 ,
  3 0 3 2 1 3 2 3 2 3 2 3 2 -> 3 2 3 3 0 0 3 1 1 2 3 1 1 1 3 1 2 ,
  3 0 3 3 1 2 3 0 0 2 2 0 1 -> 3 3 1 2 0 1 1 0 3 3 3 0 2 3 3 1 0 ,
  3 1 1 3 3 2 0 3 3 1 1 0 1 -> 3 1 1 3 3 3 1 0 2 3 1 1 3 1 3 3 3 ,
  3 2 0 3 3 1 3 2 0 2 0 0 1 -> 3 3 3 3 1 0 2 3 2 1 3 1 3 3 2 1 3 ,
  3 2 1 2 0 3 2 3 2 3 0 2 3 -> 3 3 3 1 3 2 1 0 0 2 0 0 3 0 3 3 3 ,
  3 2 2 2 0 0 2 3 2 3 1 1 1 -> 3 2 3 3 3 1 1 3 2 1 2 2 3 2 2 3 1 ,
  3 3 2 0 0 0 0 3 1 1 0 0 2 -> 3 1 2 3 3 2 1 1 1 1 2 1 2 1 0 3 1 }


The system was reversed.

After renaming modulo { 0->0, 3->1, 2->2, 1->3 }, 
it remains to prove termination of the 30-rule system
{ 0 1 1 2 1 1 2 2 0 3 0 0 0 -> 3 1 1 0 3 2 1 3 1 3 1 1 1 3 3 1 1 ,
  0 3 3 1 3 1 2 0 3 2 2 0 0 -> 0 3 3 1 2 1 2 1 1 1 1 3 2 0 3 0 3 ,
  1 1 3 0 1 3 0 3 2 0 3 3 0 -> 1 3 1 1 3 2 1 1 0 1 1 2 0 1 1 1 0 ,
  2 3 1 1 2 1 0 1 1 3 3 3 0 -> 2 0 1 2 1 1 1 0 1 2 3 2 0 3 3 1 1 ,
  3 1 3 1 3 3 3 3 0 1 3 3 0 -> 1 3 2 3 1 1 3 2 1 3 1 1 0 3 3 1 2 ,
  0 0 0 1 2 3 2 2 2 1 2 3 0 -> 3 3 0 0 1 1 3 1 2 3 1 1 0 1 1 3 3 ,
  3 1 0 3 1 2 0 0 0 0 1 2 0 -> 3 2 1 1 2 3 1 3 2 0 1 2 3 2 2 3 3 ,
  1 3 1 0 1 2 2 0 0 1 1 2 0 -> 3 2 1 3 1 1 1 0 3 0 0 3 2 1 1 3 1 ,
  0 0 1 1 1 0 1 0 1 0 1 1 0 -> 3 3 2 0 1 1 1 2 1 2 3 3 1 1 0 3 3 ,
  2 1 1 3 2 3 2 2 2 1 3 0 3 -> 3 3 1 3 1 3 1 2 1 1 1 2 0 0 3 1 1 ,
  2 0 2 1 1 0 3 0 2 1 0 3 3 -> 2 3 3 3 3 2 1 1 2 3 3 2 1 0 0 1 3 ,
  1 2 3 2 0 1 3 1 0 3 0 2 3 -> 1 1 2 1 3 1 1 1 0 0 3 0 3 1 3 1 3 ,
  0 0 3 3 2 1 2 3 3 0 3 2 3 -> 3 0 3 0 3 2 1 2 3 3 1 1 1 1 1 3 1 ,
  2 1 0 1 1 1 0 2 3 3 2 2 3 -> 2 1 2 2 1 1 3 2 1 3 1 1 1 1 3 1 3 ,
  2 2 1 0 0 1 1 1 1 1 2 2 3 -> 0 3 0 0 3 1 3 3 1 2 3 3 1 1 1 1 3 ,
  1 3 1 3 2 1 0 3 2 3 3 0 2 -> 1 1 1 3 1 3 1 2 3 1 3 2 2 0 1 1 0 ,
  0 1 2 0 0 0 1 3 2 0 2 0 2 -> 0 2 1 1 1 3 3 1 0 2 2 1 1 2 3 1 2 ,
  3 2 1 3 0 1 3 1 3 2 2 0 2 -> 3 2 0 3 3 2 0 1 2 1 1 3 1 1 3 0 2 ,
  1 2 1 2 3 2 2 1 2 0 1 3 2 -> 1 1 1 0 3 3 1 3 1 3 2 3 2 3 3 3 2 ,
  1 0 0 1 0 0 1 1 1 0 3 1 2 -> 3 1 1 1 2 3 1 1 3 1 1 1 1 2 2 3 3 ,
  3 0 2 3 0 3 1 0 2 2 3 0 1 -> 3 3 3 0 3 2 3 1 1 2 0 3 1 2 2 1 1 ,
  3 3 3 2 3 1 0 0 3 2 2 0 1 -> 3 1 2 3 1 2 0 0 3 1 2 3 1 3 1 2 1 ,
  2 0 3 0 3 3 1 1 3 2 2 0 1 -> 1 1 3 2 3 3 1 3 1 3 1 1 3 3 3 2 1 ,
  2 1 2 1 2 1 2 1 3 2 1 0 1 -> 2 3 1 3 3 3 1 2 3 3 1 0 0 1 1 2 1 ,
  3 0 2 2 0 0 1 2 3 1 1 0 1 -> 0 3 1 1 2 0 1 1 1 0 3 3 0 2 3 1 1 ,
  3 0 3 3 1 1 0 2 1 1 3 3 1 -> 1 1 1 3 1 3 3 1 2 0 3 1 1 1 3 3 1 ,
  3 0 0 2 0 2 1 3 1 1 0 2 1 -> 1 3 2 1 1 3 1 3 2 1 2 0 3 1 1 1 1 ,
  1 2 0 1 2 1 2 1 0 2 3 2 1 -> 1 1 1 0 1 0 0 2 0 0 3 2 1 3 1 1 1 ,
  3 3 3 1 2 1 2 0 0 2 2 2 1 -> 3 1 2 2 1 2 2 3 2 1 3 3 1 1 1 2 1 ,
  2 0 0 3 3 1 0 0 0 0 2 1 1 -> 3 1 0 3 2 3 2 3 3 3 3 2 1 1 2 3 1 }


Applying sparse tiling TRFC(2) [Geser/Hofbauer/Waldmann, FSCD 2019].

After renaming modulo { (0,0)->0, (0,1)->1, (1,1)->2, (1,2)->3, (2,1)->4, (2,2)->5, (2,0)->6, (0,3)->7, (3,0)->8, (3,1)->9, (1,0)->10, (3,2)->11, (1,3)->12, (3,3)->13, (0,2)->14, (0,5)->15, (1,5)->16, (2,3)->17, (4,0)->18, (4,3)->19, (3,5)->20, (4,1)->21, (4,2)->22, (2,5)->23 },
it remains to prove termination of the 750-rule system
{ 0 1 2 3 4 2 3 5 6 7 8 0 0 0 -> 7 9 2 10 7 11 4 12 9 12 9 2 2 12 13 9 2 10 ,
  0 1 2 3 4 2 3 5 6 7 8 0 0 1 -> 7 9 2 10 7 11 4 12 9 12 9 2 2 12 13 9 2 2 ,
  0 1 2 3 4 2 3 5 6 7 8 0 0 14 -> 7 9 2 10 7 11 4 12 9 12 9 2 2 12 13 9 2 3 ,
  0 1 2 3 4 2 3 5 6 7 8 0 0 7 -> 7 9 2 10 7 11 4 12 9 12 9 2 2 12 13 9 2 12 ,
  0 1 2 3 4 2 3 5 6 7 8 0 0 15 -> 7 9 2 10 7 11 4 12 9 12 9 2 2 12 13 9 2 16 ,
  10 1 2 3 4 2 3 5 6 7 8 0 0 0 -> 12 9 2 10 7 11 4 12 9 12 9 2 2 12 13 9 2 10 ,
  10 1 2 3 4 2 3 5 6 7 8 0 0 1 -> 12 9 2 10 7 11 4 12 9 12 9 2 2 12 13 9 2 2 ,
  10 1 2 3 4 2 3 5 6 7 8 0 0 14 -> 12 9 2 10 7 11 4 12 9 12 9 2 2 12 13 9 2 3 ,
  10 1 2 3 4 2 3 5 6 7 8 0 0 7 -> 12 9 2 10 7 11 4 12 9 12 9 2 2 12 13 9 2 12 ,
  10 1 2 3 4 2 3 5 6 7 8 0 0 15 -> 12 9 2 10 7 11 4 12 9 12 9 2 2 12 13 9 2 16 ,
  6 1 2 3 4 2 3 5 6 7 8 0 0 0 -> 17 9 2 10 7 11 4 12 9 12 9 2 2 12 13 9 2 10 ,
  6 1 2 3 4 2 3 5 6 7 8 0 0 1 -> 17 9 2 10 7 11 4 12 9 12 9 2 2 12 13 9 2 2 ,
  6 1 2 3 4 2 3 5 6 7 8 0 0 14 -> 17 9 2 10 7 11 4 12 9 12 9 2 2 12 13 9 2 3 ,
  6 1 2 3 4 2 3 5 6 7 8 0 0 7 -> 17 9 2 10 7 11 4 12 9 12 9 2 2 12 13 9 2 12 ,
  6 1 2 3 4 2 3 5 6 7 8 0 0 15 -> 17 9 2 10 7 11 4 12 9 12 9 2 2 12 13 9 2 16 ,
  8 1 2 3 4 2 3 5 6 7 8 0 0 0 -> 13 9 2 10 7 11 4 12 9 12 9 2 2 12 13 9 2 10 ,
  8 1 2 3 4 2 3 5 6 7 8 0 0 1 -> 13 9 2 10 7 11 4 12 9 12 9 2 2 12 13 9 2 2 ,
  8 1 2 3 4 2 3 5 6 7 8 0 0 14 -> 13 9 2 10 7 11 4 12 9 12 9 2 2 12 13 9 2 3 ,
popout
output may be truncated. 'popout' for the full output.
job log
popout
actions all output return to SRS Standard