SRS Standard pair #487515048

details

property	value
status	complete
benchmark	4487.xml
ran by	Akihisa Yamada
cpu timeout	1200 seconds
wallclock timeout	300 seconds
memory limit	137438953472 bytes
execution host	n094.star.cs.uiowa.edu
space	ICFP_2010

run statistics

property	value
solver	MultumNonMulta 3.16 29 June 2020 60G
configuration	default
runtime (wallclock)	4.54116511345 seconds
cpu usage	16.40360428
max memory	3.531169792E9

stage attributes

key	value
output-size	261537
starexec-result	YES

output

/export/starexec/sandbox2/solver/bin/starexec_run_default /export/starexec/sandbox2/benchmark/theBenchmark.xml /export/starexec/sandbox2/output/output_files


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YES

After renaming modulo { 0->0, 1->1, 4->2, 5->3, 2->4, 3->5 }, 
it remains to prove termination of the 47-rule system
{ 0 1 2 -> 3 3 2 0 4 4 0 4 3 2 ,
  0 2 1 -> 3 4 4 5 3 5 4 4 3 2 ,
  1 2 1 -> 1 2 2 4 0 5 3 2 2 3 ,
  0 1 1 1 -> 0 5 3 1 4 0 5 4 2 3 ,
  2 1 0 0 -> 1 2 0 3 2 4 3 3 5 0 ,
  2 1 1 5 -> 2 3 4 0 3 4 5 3 2 4 ,
  0 1 1 4 0 -> 5 4 5 4 5 3 2 3 4 0 ,
  0 5 0 1 5 -> 4 0 5 3 3 0 1 4 1 4 ,
  0 2 2 1 5 -> 2 3 2 3 0 3 2 3 3 4 ,
  1 0 2 1 0 -> 4 5 0 4 5 2 4 0 2 0 ,
  1 1 2 5 1 -> 1 2 4 0 3 2 2 3 3 5 ,
  0 0 0 2 5 1 -> 4 5 4 0 0 2 4 2 5 5 ,
  0 1 1 1 1 5 -> 5 1 4 5 4 5 2 1 5 5 ,
  0 1 5 2 5 1 -> 1 3 2 3 4 4 0 5 3 1 ,
  0 1 2 3 1 5 -> 4 0 3 5 4 5 1 3 0 5 ,
  0 1 3 0 0 0 -> 3 4 1 0 1 0 3 2 0 0 ,
  0 5 1 1 1 1 -> 0 5 5 1 5 0 5 4 5 5 ,
  0 5 2 0 1 0 -> 1 4 5 3 5 3 4 3 2 0 ,
  1 0 0 1 1 1 -> 1 1 3 3 5 5 5 0 0 4 ,
  1 0 3 1 5 0 -> 5 4 5 0 1 0 4 0 0 5 ,
  1 5 1 1 2 1 -> 4 3 0 5 4 3 2 3 2 2 ,
  4 3 5 2 5 4 -> 4 3 4 0 3 2 5 5 5 4 ,
  5 0 2 1 0 5 -> 3 4 5 5 0 4 1 0 5 0 ,
  5 1 0 1 3 3 -> 3 2 4 0 0 0 5 5 3 3 ,
  2 3 1 1 5 1 -> 2 2 3 3 4 4 2 3 2 0 ,
  3 1 5 2 1 4 -> 0 2 2 4 0 0 3 3 4 4 ,
  3 4 2 2 1 5 -> 3 3 3 0 3 4 4 4 1 4 ,
  0 0 0 0 2 2 5 -> 1 3 2 2 2 5 1 3 0 3 ,
  0 0 2 1 1 0 5 -> 4 1 4 0 5 3 0 1 0 5 ,
  0 5 2 1 1 0 0 -> 5 5 5 0 1 1 2 5 3 0 ,
  1 0 5 4 1 5 1 -> 4 1 5 3 3 5 3 3 1 2 ,
  1 1 0 5 3 1 5 -> 4 3 5 3 3 2 2 1 5 5 ,
  1 1 5 1 1 5 0 -> 4 5 1 4 2 3 4 0 0 0 ,
  1 1 5 2 1 5 3 -> 4 3 3 4 1 4 1 3 4 3 ,
  1 5 5 2 0 3 4 -> 2 3 2 5 2 4 3 3 4 4 ,
  1 5 2 0 2 5 4 -> 4 5 1 1 3 2 0 5 3 4 ,
  1 3 1 1 5 3 4 -> 0 1 0 5 5 4 2 5 4 4 ,
  1 3 5 1 5 2 2 -> 4 3 2 3 1 1 3 2 1 2 ,
  4 1 5 2 5 1 1 -> 3 2 2 1 2 1 2 2 1 3 ,
  5 0 2 3 0 0 2 -> 5 0 3 0 0 4 0 0 0 2 ,
  5 2 0 0 1 5 0 -> 2 2 5 0 5 4 2 4 4 0 ,
  2 0 1 2 5 4 0 -> 2 3 0 4 0 5 5 5 5 0 ,
  2 0 2 0 5 2 2 -> 2 2 2 5 3 1 2 1 2 2 ,
  2 0 2 5 4 1 0 -> 1 2 4 5 3 3 5 4 5 3 ,
  3 1 5 2 1 5 1 -> 1 3 2 2 5 2 5 0 1 4 ,
  3 1 2 2 5 0 0 -> 3 0 4 3 2 4 3 4 4 0 ,
  3 3 0 0 2 1 3 -> 3 2 5 4 0 4 3 3 3 3 }


Applying sparse tiling TRFC(2) [Geser/Hofbauer/Waldmann, FSCD 2019].

After renaming modulo { (0,0)->0, (0,1)->1, (1,2)->2, (2,0)->3, (0,3)->4, (3,3)->5, (3,2)->6, (0,4)->7, (4,4)->8, (4,0)->9, (4,3)->10, (2,1)->11, (2,2)->12, (2,3)->13, (2,4)->14, (2,5)->15, (2,7)->16, (1,0)->17, (1,3)->18, (3,0)->19, (5,0)->20, (5,3)->21, (6,0)->22, (6,3)->23, (0,2)->24, (3,4)->25, (4,5)->26, (3,5)->27, (5,4)->28, (1,1)->29, (1,4)->30, (1,5)->31, (1,7)->32, (0,5)->33, (3,1)->34, (3,7)->35, (4,1)->36, (5,1)->37, (6,1)->38, (4,2)->39, (0,7)->40, (5,2)->41, (6,2)->42, (5,5)->43, (5,7)->44, (4,7)->45, (6,5)->46, (6,4)->47 },
it remains to prove termination of the 2303-rule system
{ 0 1 2 3 -> 4 5 6 3 7 8 9 7 10 6 3 ,
  0 1 2 11 -> 4 5 6 3 7 8 9 7 10 6 11 ,
  0 1 2 12 -> 4 5 6 3 7 8 9 7 10 6 12 ,
  0 1 2 13 -> 4 5 6 3 7 8 9 7 10 6 13 ,
  0 1 2 14 -> 4 5 6 3 7 8 9 7 10 6 14 ,
  0 1 2 15 -> 4 5 6 3 7 8 9 7 10 6 15 ,
  0 1 2 16 -> 4 5 6 3 7 8 9 7 10 6 16 ,
  17 1 2 3 -> 18 5 6 3 7 8 9 7 10 6 3 ,
  17 1 2 11 -> 18 5 6 3 7 8 9 7 10 6 11 ,
  17 1 2 12 -> 18 5 6 3 7 8 9 7 10 6 12 ,
  17 1 2 13 -> 18 5 6 3 7 8 9 7 10 6 13 ,
  17 1 2 14 -> 18 5 6 3 7 8 9 7 10 6 14 ,
  17 1 2 15 -> 18 5 6 3 7 8 9 7 10 6 15 ,
  17 1 2 16 -> 18 5 6 3 7 8 9 7 10 6 16 ,
  3 1 2 3 -> 13 5 6 3 7 8 9 7 10 6 3 ,
  3 1 2 11 -> 13 5 6 3 7 8 9 7 10 6 11 ,
  3 1 2 12 -> 13 5 6 3 7 8 9 7 10 6 12 ,
  3 1 2 13 -> 13 5 6 3 7 8 9 7 10 6 13 ,
  3 1 2 14 -> 13 5 6 3 7 8 9 7 10 6 14 ,
  3 1 2 15 -> 13 5 6 3 7 8 9 7 10 6 15 ,
  3 1 2 16 -> 13 5 6 3 7 8 9 7 10 6 16 ,
  19 1 2 3 -> 5 5 6 3 7 8 9 7 10 6 3 ,
  19 1 2 11 -> 5 5 6 3 7 8 9 7 10 6 11 ,
  19 1 2 12 -> 5 5 6 3 7 8 9 7 10 6 12 ,
  19 1 2 13 -> 5 5 6 3 7 8 9 7 10 6 13 ,
  19 1 2 14 -> 5 5 6 3 7 8 9 7 10 6 14 ,
  19 1 2 15 -> 5 5 6 3 7 8 9 7 10 6 15 ,
  19 1 2 16 -> 5 5 6 3 7 8 9 7 10 6 16 ,
  9 1 2 3 -> 10 5 6 3 7 8 9 7 10 6 3 ,
  9 1 2 11 -> 10 5 6 3 7 8 9 7 10 6 11 ,
  9 1 2 12 -> 10 5 6 3 7 8 9 7 10 6 12 ,
  9 1 2 13 -> 10 5 6 3 7 8 9 7 10 6 13 ,
  9 1 2 14 -> 10 5 6 3 7 8 9 7 10 6 14 ,
  9 1 2 15 -> 10 5 6 3 7 8 9 7 10 6 15 ,
  9 1 2 16 -> 10 5 6 3 7 8 9 7 10 6 16 ,
  20 1 2 3 -> 21 5 6 3 7 8 9 7 10 6 3 ,
  20 1 2 11 -> 21 5 6 3 7 8 9 7 10 6 11 ,

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job log

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