SRS Standard pair #487516482

details

property	value
status	complete
benchmark	86577.xml
ran by	Akihisa Yamada
cpu timeout	1200 seconds
wallclock timeout	300 seconds
memory limit	137438953472 bytes
execution host	n122.star.cs.uiowa.edu
space	ICFP_2010

run statistics

property	value
solver	MultumNonMulta 3.16 29 June 2020 60G
configuration	default
runtime (wallclock)	164.873768091 seconds
cpu usage	654.98787449
max memory	2.8380717056E10

stage attributes

key	value
output-size	476041
starexec-result	YES

output

/export/starexec/sandbox2/solver/bin/starexec_run_default /export/starexec/sandbox2/benchmark/theBenchmark.xml /export/starexec/sandbox2/output/output_files


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YES

After renaming modulo { 0->0, 1->1, 2->2, 3->3, 4->4, 5->5 }, 
it remains to prove termination of the 30-rule system
{ 0 0 1 1 -> 0 2 1 ,
  0 0 3 3 0 0 -> 0 0 4 0 4 0 ,
  1 5 5 2 1 0 -> 1 5 4 3 1 0 ,
  4 0 3 4 2 2 -> 4 5 2 2 3 ,
  2 2 4 1 3 4 1 -> 5 2 4 5 3 ,
  0 3 1 5 2 3 1 5 -> 0 3 3 5 3 5 1 5 ,
  3 1 5 1 5 0 4 2 -> 3 1 4 5 0 5 2 ,
  3 0 0 2 2 0 4 4 0 -> 2 5 5 0 2 0 2 0 ,
  3 0 1 3 1 5 1 4 2 -> 1 1 2 4 2 4 1 0 2 ,
  3 0 4 4 0 2 4 4 4 -> 2 5 5 0 3 3 4 ,
  0 2 5 2 4 3 4 0 4 3 -> 0 3 5 3 1 3 4 0 3 ,
  1 4 5 3 1 1 1 0 3 2 -> 1 3 2 5 3 5 2 1 ,
  2 4 0 4 5 3 3 3 2 0 -> 0 3 1 5 4 5 5 0 ,
  1 3 2 1 5 1 1 0 5 2 2 -> 1 0 2 5 4 2 2 0 5 3 ,
  3 2 4 0 1 0 0 2 0 1 3 -> 2 4 0 3 5 5 1 3 3 ,
  4 4 1 0 1 3 3 1 4 1 2 -> 3 1 2 4 4 4 2 1 2 2 ,
  4 0 4 2 2 0 4 2 1 4 1 4 -> 4 5 0 5 4 5 5 4 ,
  4 3 5 4 3 4 0 0 4 2 5 0 -> 4 0 2 0 3 3 3 5 3 1 2 4 ,
  2 5 5 1 5 1 2 0 2 1 3 3 4 -> 3 1 1 1 2 5 2 1 4 0 0 4 4 ,
  3 4 1 1 3 1 1 1 5 4 3 4 1 -> 3 4 0 0 3 5 3 5 0 4 4 4 ,
  1 1 2 0 2 4 1 1 3 3 3 5 1 3 -> 5 1 3 4 5 1 1 0 3 4 0 2 0 ,
  1 4 0 0 5 2 2 5 2 2 3 0 2 5 -> 1 5 4 2 3 0 1 3 0 3 2 2 0 5 ,
  2 2 0 2 0 0 5 3 2 3 2 0 3 2 -> 4 5 1 5 3 3 3 4 4 2 0 4 ,
  4 2 3 5 4 2 5 5 1 1 4 4 0 4 1 0 -> 4 1 2 5 4 0 5 3 2 5 0 4 2 4 0 ,
  5 0 3 4 0 0 0 4 3 4 2 4 3 3 2 0 4 -> 5 2 3 3 1 2 0 4 3 0 1 5 5 2 3 4 ,
  5 5 4 4 0 5 5 2 4 0 5 1 2 3 2 4 0 -> 0 3 2 0 4 3 1 2 4 5 3 3 0 1 1 5 1 3 ,
  0 1 4 3 5 3 0 4 1 1 2 3 3 1 4 0 5 2 3 -> 0 3 0 0 5 4 5 0 4 0 2 2 1 4 0 0 0 4 ,
  4 2 1 0 0 4 4 4 3 0 5 1 3 1 2 3 5 1 0 2 -> 4 4 1 4 5 0 4 2 4 5 2 3 4 2 2 5 5 1 ,
  4 4 4 1 4 5 2 2 0 1 4 5 2 2 1 4 5 0 0 4 -> 2 1 2 1 4 0 4 5 3 2 5 0 3 2 0 2 2 5 1 4 ,
  5 3 2 0 4 1 4 1 4 2 5 2 3 4 4 4 3 2 5 2 4 -> 5 0 4 3 0 0 2 1 5 4 4 2 5 3 4 3 0 5 5 }


Applying sparse tiling TRFC(2) [Geser/Hofbauer/Waldmann, FSCD 2019].

After renaming modulo { (0,0)->0, (0,1)->1, (1,1)->2, (1,0)->3, (0,2)->4, (2,1)->5, (1,2)->6, (1,3)->7, (1,4)->8, (1,5)->9, (1,7)->10, (2,0)->11, (3,0)->12, (4,0)->13, (5,0)->14, (6,0)->15, (0,3)->16, (3,3)->17, (0,4)->18, (0,5)->19, (0,7)->20, (5,5)->21, (5,2)->22, (5,4)->23, (4,3)->24, (3,1)->25, (4,1)->26, (5,1)->27, (6,1)->28, (3,4)->29, (4,2)->30, (2,2)->31, (4,5)->32, (2,3)->33, (3,2)->34, (2,4)->35, (2,5)->36, (3,5)->37, (2,7)->38, (3,7)->39, (4,4)->40, (6,4)->41, (5,3)->42, (6,2)->43, (6,5)->44, (5,7)->45, (6,3)->46, (4,7)->47 },
it remains to prove termination of the 1470-rule system
{ 0 0 1 2 3 -> 0 4 5 3 ,
  0 0 1 2 2 -> 0 4 5 2 ,
  0 0 1 2 6 -> 0 4 5 6 ,
  0 0 1 2 7 -> 0 4 5 7 ,
  0 0 1 2 8 -> 0 4 5 8 ,
  0 0 1 2 9 -> 0 4 5 9 ,
  0 0 1 2 10 -> 0 4 5 10 ,
  3 0 1 2 3 -> 3 4 5 3 ,
  3 0 1 2 2 -> 3 4 5 2 ,
  3 0 1 2 6 -> 3 4 5 6 ,
  3 0 1 2 7 -> 3 4 5 7 ,
  3 0 1 2 8 -> 3 4 5 8 ,
  3 0 1 2 9 -> 3 4 5 9 ,
  3 0 1 2 10 -> 3 4 5 10 ,
  11 0 1 2 3 -> 11 4 5 3 ,
  11 0 1 2 2 -> 11 4 5 2 ,
  11 0 1 2 6 -> 11 4 5 6 ,
  11 0 1 2 7 -> 11 4 5 7 ,
  11 0 1 2 8 -> 11 4 5 8 ,
  11 0 1 2 9 -> 11 4 5 9 ,
  11 0 1 2 10 -> 11 4 5 10 ,
  12 0 1 2 3 -> 12 4 5 3 ,
  12 0 1 2 2 -> 12 4 5 2 ,
  12 0 1 2 6 -> 12 4 5 6 ,
  12 0 1 2 7 -> 12 4 5 7 ,
  12 0 1 2 8 -> 12 4 5 8 ,
  12 0 1 2 9 -> 12 4 5 9 ,
  12 0 1 2 10 -> 12 4 5 10 ,
  13 0 1 2 3 -> 13 4 5 3 ,
  13 0 1 2 2 -> 13 4 5 2 ,
  13 0 1 2 6 -> 13 4 5 6 ,
  13 0 1 2 7 -> 13 4 5 7 ,
  13 0 1 2 8 -> 13 4 5 8 ,
  13 0 1 2 9 -> 13 4 5 9 ,
  13 0 1 2 10 -> 13 4 5 10 ,
  14 0 1 2 3 -> 14 4 5 3 ,
  14 0 1 2 2 -> 14 4 5 2 ,
  14 0 1 2 6 -> 14 4 5 6 ,
  14 0 1 2 7 -> 14 4 5 7 ,
  14 0 1 2 8 -> 14 4 5 8 ,
  14 0 1 2 9 -> 14 4 5 9 ,
  14 0 1 2 10 -> 14 4 5 10 ,
  15 0 1 2 3 -> 15 4 5 3 ,
  15 0 1 2 2 -> 15 4 5 2 ,
  15 0 1 2 6 -> 15 4 5 6 ,
  15 0 1 2 7 -> 15 4 5 7 ,
  15 0 1 2 8 -> 15 4 5 8 ,
  15 0 1 2 9 -> 15 4 5 9 ,
  15 0 1 2 10 -> 15 4 5 10 ,
  0 0 16 17 12 0 0 -> 0 0 18 13 18 13 0 ,
  0 0 16 17 12 0 1 -> 0 0 18 13 18 13 1 ,
  0 0 16 17 12 0 4 -> 0 0 18 13 18 13 4 ,
  0 0 16 17 12 0 16 -> 0 0 18 13 18 13 16 ,
  0 0 16 17 12 0 18 -> 0 0 18 13 18 13 18 ,

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