details

property	value
status	complete
benchmark	abaaaaaaa-aaaaaaaabab.srs.xml
ran by	Akihisa Yamada
cpu timeout	1200 seconds
wallclock timeout	300 seconds
memory limit	137438953472 bytes
execution host	n011.star.cs.uiowa.edu
space	Wenzel_16

run statistics

property	value
solver	matchbox-2020-06-25
configuration	tc20-std.sh
runtime (wallclock)	75.0130319595 seconds
cpu usage	299.105712913
max memory	4.395061248E9

stage attributes

key	value
output-size	6823
starexec-result	YES

output

/export/starexec/sandbox2/solver/bin/starexec_run_tc20-std.sh /export/starexec/sandbox2/benchmark/theBenchmark.xml /export/starexec/sandbox2/output/output_files -------------------------------------------------------------------------------- YES ************************************************** summary ************************************************** SRS with 1 rules on 2 letters DP SRS with 9 strict rules and 1 weak rules on 3 letters EDG SRS with 9 strict rules and 1 weak rules on 3 letters Matrix { monotone = Weak, domain = Arctic, shape = Full, bits = 4, dim = 2, solver = Minisatapi, verbose = False, tracing = False} SRS with 2 strict rules and 1 weak rules on 3 letters EDG SRS with 2 strict rules and 1 weak rules on 3 letters Matrix { monotone = Weak, domain = Arctic, shape = Full, bits = 3, dim = 7, solver = Minisatapi, verbose = False, tracing = False} SRS with 0 strict rules and 1 weak rules on 2 letters EDG ************************************************** proof ************************************************** property Termination has value Just True for SRS [a, b, a, a, a, a, a, a, a] -> [a, a, a, a, a, a, a, a, b, a, b] {- Input 0 -} reason DP property Termination has value Just True for SRS [a, b, a, a, a, a, a, a, a] ->= [ a , a , a , a , a , a , a , a , b , a , b ] {- DP Nontop (Input 0) -} [a#, b, a, a, a, a, a, a, a] |-> [ a# , a , a , a , a , a , a , a , b , a , b ] {- DP (Top 0) (Input 0) -} [a#, b, a, a, a, a, a, a, a] |-> [ a# , a , a , a , a , a , a , b , a , b ] {- DP (Top 1) (Input 0) -} [a#, b, a, a, a, a, a, a, a] |-> [ a# , a , a , a , a , a , b , a , b ] {- DP (Top 2) (Input 0) -} [a#, b, a, a, a, a, a, a, a] |-> [ a# , a , a , a , a , b , a , b ] {- DP (Top 3) (Input 0) -} [a#, b, a, a, a, a, a, a, a] |-> [ a# , a , a , a , b , a , b ] {- DP (Top 4) (Input 0) -} [a#, b, a, a, a, a, a, a, a] |-> [a#, a, a, b, a, b] {- DP (Top 5) (Input 0) -} [a#, b, a, a, a, a, a, a, a] |-> [a#, a, b, a, b] {- DP (Top 6) (Input 0) -} [a#, b, a, a, a, a, a, a, a] |-> [a#, b] {- DP (Top 9) (Input 0) -} [a#, b, a, a, a, a, a, a, a] |-> [a#, b, a, b] {- DP (Top 7) (Input 0) -} reason EDG property Termination has value Just True for SRS [a#, b, a, a, a, a, a, a, a] |-> [ a# , a , a , a , a , a , a , a , b , a , b ] {- DP (Top 0) (Input 0) -} [a#, b, a, a, a, a, a, a, a] |-> [a#, b, a, b] {- DP (Top 7) (Input 0) -} [a#, b, a, a, a, a, a, a, a] |-> [a#, b] {- DP (Top 9) (Input 0) -} [a#, b, a, a, a, a, a, a, a] |-> [a#, a, b, a, b] {- DP (Top 6) (Input 0) -} [a#, b, a, a, a, a, a, a, a] |-> [a#, a, a, b, a, b] {- DP (Top 5) (Input 0) -} [a#, b, a, a, a, a, a, a, a] |-> [ a# , a , a , a , b , a , b ] {- DP (Top 4) (Input 0) -} [a#, b, a, a, a, a, a, a, a] |-> [ a# , a , a , a , a , b , a , b ] {- DP (Top 3) (Input 0) -} [a#, b, a, a, a, a, a, a, a] |-> [ a# , a , a , a , a , a , b , a , b ] {- DP (Top 2) (Input 0) -} [a#, b, a, a, a, a, a, a, a] |-> [ a# , a , a , a , a , a , a , b , a , b ] {- DP (Top 1) (Input 0) -} [a, b, a, a, a, a, a, a, a] ->= [ a , a , a , a , a , a , a , a , b , a , b ] {- DP Nontop (Input 0) -} reason ( a , Wk / 0A 0A \ \ -2A -2A / ) ( b , Wk / 0A 0A \ \ 0A 0A / ) ( a# , Wk / 11A 13A \ \ 11A 13A / ) property Termination has value Just True for SRS [a#, b, a, a, a, a, a, a, a] |-> [a#, b, a, b] {- DP (Top 7) (Input 0) -} [a#, b, a, a, a, a, a, a, a] |-> [a#, b] {- DP (Top 9) (Input 0) -} [a, b, a, a, a, a, a, a, a] ->= [ a , a , a , a , a , a , a , a , b , a , b ] {- DP Nontop (Input 0) -} reason EDG property Termination has value Just True for SRS [a#, b, a, a, a, a, a, a, a] |-> [a#, b, a, b] {- DP (Top 7) (Input 0) -} [a#, b, a, a, a, a, a, a, a] |-> [a#, b] {- DP (Top 9) (Input 0) -} [a, b, a, a, a, a, a, a, a] ->= [ a , a , a , a , a , a , a , a , b , a , b ] {- DP Nontop (Input 0) -} reason ( a , Wk / 0A 7A 7A 7A 7A 7A 7A \ | 0A 0A 7A 7A 7A 7A 7A | | 0A 0A 0A 7A 7A 7A 7A | | 0A 0A 0A 0A 7A 7A 7A | | 0A 0A 0A 0A 0A 7A 7A | | 0A 0A 0A 0A 0A 0A 7A | \ 0A 0A 0A 0A 0A 0A 0A / ) ( b , Wk / 0A 0A 0A 0A 0A 0A 0A \ | -7A -7A -7A -7A -7A -7A -7A | | -7A -7A -7A -7A -7A -7A -7A | | -7A -7A -7A -7A -7A -7A -7A | | -7A -7A -7A -7A -7A -7A -7A | | -7A -7A -7A -7A -7A -7A -7A | \ -7A -7A -7A -7A -7A -7A -7A / ) ( a# , Wk / 1A 1A 3A 8A 8A 8A 8A \ | 1A 1A 3A 8A 8A 8A 8A | | 1A 1A 3A 8A 8A 8A 8A | | 1A 1A 3A 8A 8A 8A 8A | popout

output may be truncated. 'popout' for the full output.

job log

popout

actions

all output return to SRS Standard