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SRS Standard pair #487520020
details
property
value
status
complete
benchmark
z009.xml
ran by
Akihisa Yamada
cpu timeout
1200 seconds
wallclock timeout
300 seconds
memory limit
137438953472 bytes
execution host
n178.star.cs.uiowa.edu
space
Zantema_04
run statistics
property
value
solver
matchbox-2020-06-25
configuration
tc20-std.sh
runtime (wallclock)
2.20750594139 seconds
cpu usage
8.316150534
max memory
3.59927808E8
stage attributes
key
value
output-size
7238
starexec-result
YES
output
/export/starexec/sandbox2/solver/bin/starexec_run_tc20-std.sh /export/starexec/sandbox2/benchmark/theBenchmark.xml /export/starexec/sandbox2/output/output_files -------------------------------------------------------------------------------- YES ************************************************** summary ************************************************** SRS with 4 rules on 4 letters mirror SRS with 4 rules on 4 letters DP SRS with 7 strict rules and 4 weak rules on 7 letters weights SRS with 3 strict rules and 4 weak rules on 6 letters EDG SRS with 3 strict rules and 4 weak rules on 6 letters Matrix { monotone = Weak, domain = Arctic, shape = Full, bits = 4, dim = 2, solver = Minisatapi, verbose = False, tracing = False} SRS with 2 strict rules and 4 weak rules on 6 letters EDG SRS with 2 strict rules and 4 weak rules on 6 letters Matrix { monotone = Weak, domain = Arctic, shape = Full, bits = 4, dim = 2, solver = Minisatapi, verbose = False, tracing = False} SRS with 1 strict rules and 4 weak rules on 6 letters weights SRS with 0 strict rules and 4 weak rules on 4 letters EDG ************************************************** proof ************************************************** property Termination has value Just True for SRS [a] -> [b, c] {- Input 0 -} [a, b] -> [b, a] {- Input 1 -} [d, c] -> [d, a] {- Input 2 -} [a, c] -> [c, a] {- Input 3 -} reason mirror property Termination has value Just True for SRS [a] -> [c, b] {- Mirror (Input 0) -} [b, a] -> [a, b] {- Mirror (Input 1) -} [c, d] -> [a, d] {- Mirror (Input 2) -} [c, a] -> [a, c] {- Mirror (Input 3) -} reason DP property Termination has value Just True for SRS [a] ->= [c, b] {- DP Nontop (Mirror (Input 0)) -} [b, a] ->= [a, b] {- DP Nontop (Mirror (Input 1)) -} [c, d] ->= [a, d] {- DP Nontop (Mirror (Input 2)) -} [c, a] ->= [a, c] {- DP Nontop (Mirror (Input 3)) -} [a#] |-> [b#] {- DP (Top 1) (Mirror (Input 0)) -} [a#] |-> [c#, b] {- DP (Top 0) (Mirror (Input 0)) -} [b#, a] |-> [a#, b] {- DP (Top 0) (Mirror (Input 1)) -} [b#, a] |-> [b#] {- DP (Top 1) (Mirror (Input 1)) -} [c#, a] |-> [a#, c] {- DP (Top 0) (Mirror (Input 3)) -} [c#, a] |-> [c#] {- DP (Top 1) (Mirror (Input 3)) -} [c#, d] |-> [a#, d] {- DP (Top 0) (Mirror (Input 2)) -} reason (a, 2/1) (c, 2/1) (a#, 1/1) (c#, 1/1) property Termination has value Just True for SRS [a] ->= [c, b] {- DP Nontop (Mirror (Input 0)) -} [b, a] ->= [a, b] {- DP Nontop (Mirror (Input 1)) -} [c, d] ->= [a, d] {- DP Nontop (Mirror (Input 2)) -} [c, a] ->= [a, c] {- DP Nontop (Mirror (Input 3)) -} [a#] |-> [c#, b] {- DP (Top 0) (Mirror (Input 0)) -} [c#, a] |-> [a#, c] {- DP (Top 0) (Mirror (Input 3)) -} [c#, d] |-> [a#, d] {- DP (Top 0) (Mirror (Input 2)) -} reason EDG property Termination has value Just True for SRS [a#] |-> [c#, b] {- DP (Top 0) (Mirror (Input 0)) -} [c#, d] |-> [a#, d] {- DP (Top 0) (Mirror (Input 2)) -} [c#, a] |-> [a#, c] {- DP (Top 0) (Mirror (Input 3)) -} [a] ->= [c, b] {- DP Nontop (Mirror (Input 0)) -} [b, a] ->= [a, b] {- DP Nontop (Mirror (Input 1)) -} [c, d] ->= [a, d] {- DP Nontop (Mirror (Input 2)) -} [c, a] ->= [a, c] {- DP Nontop (Mirror (Input 3)) -} reason ( a , Wk / 14A 14A \ \ 12A 14A / ) ( c , Wk / 14A 16A \ \ 12A 14A / ) ( b , Wk / 0A 0A \ \ -2A -2A / ) ( d , Wk / 10A 10A \ \ 10A 10A / ) ( a# , Wk / 2A 2A \ \ 2A 2A / ) ( c# , Wk / 2A 4A \
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