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SRS Standard pair #487520033
details
property
value
status
complete
benchmark
z072.xml
ran by
Akihisa Yamada
cpu timeout
1200 seconds
wallclock timeout
300 seconds
memory limit
137438953472 bytes
execution host
n012.star.cs.uiowa.edu
space
Zantema_04
run statistics
property
value
solver
AProVE
configuration
standard
runtime (wallclock)
1.80186104774 seconds
cpu usage
3.69222638
max memory
2.62066176E8
stage attributes
key
value
output-size
2557
starexec-result
YES
output
/export/starexec/sandbox/solver/bin/starexec_run_standard /export/starexec/sandbox/benchmark/theBenchmark.xml /export/starexec/sandbox/output/output_files -------------------------------------------------------------------------------- YES proof of /export/starexec/sandbox/benchmark/theBenchmark.xml # AProVE Commit ID: 794c25de1cacf0d048858bcd21c9a779e1221865 marcel 20200619 unpublished dirty Termination w.r.t. Q of the given QTRS could be proven: (0) QTRS (1) RFCMatchBoundsTRSProof [EQUIVALENT, 19 ms] (2) YES ---------------------------------------- (0) Obligation: Q restricted rewrite system: The TRS R consists of the following rules: a(l(x1)) -> l(a(x1)) r(a(a(x1))) -> a(a(r(x1))) b(l(x1)) -> b(a(r(x1))) r(b(x1)) -> l(b(x1)) Q is empty. ---------------------------------------- (1) RFCMatchBoundsTRSProof (EQUIVALENT) Termination of the TRS R could be shown with a Match Bound [MATCHBOUNDS1,MATCHBOUNDS2] of 3. This implies Q-termination of R. The following rules were used to construct the certificate: a(l(x1)) -> l(a(x1)) r(a(a(x1))) -> a(a(r(x1))) b(l(x1)) -> b(a(r(x1))) r(b(x1)) -> l(b(x1)) The certificate found is represented by the following graph. The certificate consists of the following enumerated nodes: 1, 3, 5, 6, 7, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 39, 40 Node 1 is start node and node 3 is final node. Those nodes are connected through the following edges: * 1 to 5 labelled l_1(0)* 1 to 6 labelled a_1(0), b_1(0)* 1 to 16 labelled l_1(1)* 1 to 17 labelled b_1(1)* 3 to 3 labelled #_1(0)* 5 to 3 labelled a_1(0), b_1(0)* 5 to 11 labelled l_1(1)* 5 to 12 labelled b_1(1)* 5 to 20 labelled b_1(2)* 6 to 7 labelled a_1(0)* 6 to 15 labelled l_1(1)* 7 to 3 labelled r_1(0)* 7 to 12 labelled a_1(1)* 7 to 14 labelled l_1(1)* 7 to 22 labelled l_1(2)* 11 to 3 labelled a_1(1)* 11 to 11 labelled l_1(1)* 12 to 13 labelled a_1(1)* 12 to 19 labelled l_1(2)* 13 to 3 labelled r_1(1)* 13 to 12 labelled a_1(1)* 13 to 14 labelled l_1(1)* 13 to 22 labelled l_1(2)* 14 to 3 labelled b_1(1)* 14 to 12 labelled b_1(1)* 14 to 20 labelled b_1(2)* 15 to 14 labelled a_1(1)* 15 to 22 labelled a_1(1)* 16 to 15 labelled a_1(1)* 17 to 18 labelled a_1(1)* 18 to 15 labelled r_1(1)* 18 to 20 labelled a_1(2)* 19 to 14 labelled a_1(2)* 19 to 22 labelled a_1(2)* 20 to 21 labelled a_1(2)* 21 to 19 labelled r_1(2)* 21 to 39 labelled a_1(3)* 22 to 19 labelled a_1(2)* 39 to 40 labelled a_1(3)* 40 to 19 labelled r_1(3)* 40 to 39 labelled a_1(3) ---------------------------------------- (2) YES
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