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SRS Standard pair #487520046
details
property
value
status
complete
benchmark
z018.xml
ran by
Akihisa Yamada
cpu timeout
1200 seconds
wallclock timeout
300 seconds
memory limit
137438953472 bytes
execution host
n028.star.cs.uiowa.edu
space
Zantema_04
run statistics
property
value
solver
MultumNonMulta 3.16 29 June 2020 60G
configuration
default
runtime (wallclock)
0.516779899597 seconds
cpu usage
0.628297626
max memory
3.42667264E8
stage attributes
key
value
output-size
1138
starexec-result
YES
output
/export/starexec/sandbox2/solver/bin/starexec_run_default /export/starexec/sandbox2/benchmark/theBenchmark.xml /export/starexec/sandbox2/output/output_files -------------------------------------------------------------------------------- YES After renaming modulo { a->0, b->1, c->2 }, it remains to prove termination of the 3-rule system { 0 1 -> 1 2 0 , 1 2 -> 2 1 1 , 1 0 -> 0 2 1 } The system was reversed. After renaming modulo { 1->0, 0->1, 2->2 }, it remains to prove termination of the 3-rule system { 0 1 -> 1 2 0 , 2 0 -> 0 0 2 , 1 0 -> 0 2 1 } Applying sparse untiling TRFCU(2) after reversal [Geser/Hofbauer/Waldmann, FSCD 2019]. After renaming modulo { 1->0, 2->1, 0->2 }, it remains to prove termination of the 2-rule system { 0 1 -> 1 0 0 , 0 2 -> 2 1 0 } Applying sparse untiling TRFCU(2) [Geser/Hofbauer/Waldmann, FSCD 2019]. After renaming modulo { 0->0, 1->1 }, it remains to prove termination of the 1-rule system { 0 1 -> 1 1 0 } Applying sparse untiling TRFCU(2) [Geser/Hofbauer/Waldmann, FSCD 2019]. After renaming modulo { }, it remains to prove termination of the 0-rule system { }
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