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SRS Standard pair #487520056
details
property
value
status
complete
benchmark
z011.xml
ran by
Akihisa Yamada
cpu timeout
1200 seconds
wallclock timeout
300 seconds
memory limit
137438953472 bytes
execution host
n031.star.cs.uiowa.edu
space
Zantema_04
run statistics
property
value
solver
matchbox-2020-06-25
configuration
tc20-std.sh
runtime (wallclock)
3.88441085815 seconds
cpu usage
14.985119523
max memory
5.53447424E8
stage attributes
key
value
output-size
9025
starexec-result
YES
output
/export/starexec/sandbox2/solver/bin/starexec_run_tc20-std.sh /export/starexec/sandbox2/benchmark/theBenchmark.xml /export/starexec/sandbox2/output/output_files -------------------------------------------------------------------------------- YES ************************************************** summary ************************************************** SRS with 3 rules on 3 letters mirror SRS with 3 rules on 3 letters DP SRS with 9 strict rules and 3 weak rules on 6 letters weights SRS with 7 strict rules and 3 weak rules on 6 letters EDG SRS with 7 strict rules and 3 weak rules on 6 letters Matrix { monotone = Strict, domain = Natural, shape = Full, bits = 3, dim = 2, solver = Minisatapi, verbose = False, tracing = False} SRS with 5 strict rules and 3 weak rules on 6 letters EDG SRS with 5 strict rules and 3 weak rules on 6 letters Matrix { monotone = Weak, domain = Arctic, shape = Full, bits = 4, dim = 2, solver = Minisatapi, verbose = False, tracing = False} SRS with 4 strict rules and 3 weak rules on 6 letters weights SRS with 1 strict rules and 3 weak rules on 4 letters EDG SRS with 1 strict rules and 3 weak rules on 4 letters Matrix { monotone = Weak, domain = Natural, shape = Full, bits = 5, dim = 2, solver = Minisatapi, verbose = False, tracing = False} SRS with 0 strict rules and 3 weak rules on 3 letters EDG ************************************************** proof ************************************************** property Termination has value Just True for SRS [a, b] -> [b, b, a] {- Input 0 -} [b, c] -> [c, b, b] {- Input 1 -} [c, a] -> [a, c, c] {- Input 2 -} reason mirror property Termination has value Just True for SRS [b, a] -> [a, b, b] {- Mirror (Input 0) -} [c, b] -> [b, b, c] {- Mirror (Input 1) -} [a, c] -> [c, c, a] {- Mirror (Input 2) -} reason DP property Termination has value Just True for SRS [b, a] ->= [a, b, b] {- DP Nontop (Mirror (Input 0)) -} [c, b] ->= [b, b, c] {- DP Nontop (Mirror (Input 1)) -} [a, c] ->= [c, c, a] {- DP Nontop (Mirror (Input 2)) -} [a#, c] |-> [a#] {- DP (Top 2) (Mirror (Input 2)) -} [a#, c] |-> [c#, a] {- DP (Top 1) (Mirror (Input 2)) -} [a#, c] |-> [c#, c, a] {- DP (Top 0) (Mirror (Input 2)) -} [b#, a] |-> [a#, b, b] {- DP (Top 0) (Mirror (Input 0)) -} [b#, a] |-> [b#] {- DP (Top 2) (Mirror (Input 0)) -} [b#, a] |-> [b#, b] {- DP (Top 1) (Mirror (Input 0)) -} [c#, b] |-> [b#, b, c] {- DP (Top 0) (Mirror (Input 1)) -} [c#, b] |-> [b#, c] {- DP (Top 1) (Mirror (Input 1)) -} [c#, b] |-> [c#] {- DP (Top 2) (Mirror (Input 1)) -} reason (a, 1/2) (a#, 1/2) property Termination has value Just True for SRS [b, a] ->= [a, b, b] {- DP Nontop (Mirror (Input 0)) -} [c, b] ->= [b, b, c] {- DP Nontop (Mirror (Input 1)) -} [a, c] ->= [c, c, a] {- DP Nontop (Mirror (Input 2)) -} [a#, c] |-> [a#] {- DP (Top 2) (Mirror (Input 2)) -} [a#, c] |-> [c#, a] {- DP (Top 1) (Mirror (Input 2)) -} [a#, c] |-> [c#, c, a] {- DP (Top 0) (Mirror (Input 2)) -} [b#, a] |-> [a#, b, b] {- DP (Top 0) (Mirror (Input 0)) -} [c#, b] |-> [b#, b, c] {- DP (Top 0) (Mirror (Input 1)) -} [c#, b] |-> [b#, c] {- DP (Top 1) (Mirror (Input 1)) -} [c#, b] |-> [c#] {- DP (Top 2) (Mirror (Input 1)) -} reason EDG property Termination has value Just True for SRS [a#, c] |-> [a#] {- DP (Top 2) (Mirror (Input 2)) -} [a#, c] |-> [c#, c, a] {- DP (Top 0) (Mirror (Input 2)) -} [c#, b] |-> [c#] {- DP (Top 2) (Mirror (Input 1)) -} [c#, b] |-> [b#, c] {- DP (Top 1) (Mirror (Input 1)) -} [b#, a] |-> [a#, b, b] {- DP (Top 0) (Mirror (Input 0)) -} [a#, c] |-> [c#, a] {- DP (Top 1) (Mirror (Input 2)) -} [c#, b] |-> [b#, b, c] {- DP (Top 0) (Mirror (Input 1)) -} [b, a] ->= [a, b, b] {- DP Nontop (Mirror (Input 0)) -} [c, b] ->= [b, b, c] {- DP Nontop (Mirror (Input 1)) -} [a, c] ->= [c, c, a] {- DP Nontop (Mirror (Input 2)) -} reason ( b , St / 1 0 \ \ 0 1 / ) ( a , St / 2 1 \ \ 0 1 / ) ( c , St / 1 1 \ \ 0 1 / ) ( a# , St / 2 1 \ \ 0 1 / )
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