details

property	value
status	complete
benchmark	356.xml
ran by	Akihisa Yamada
cpu timeout	1200 seconds
wallclock timeout	300 seconds
memory limit	137438953472 bytes
execution host	n184.star.cs.uiowa.edu
space	COPS

run statistics

property	value
solver	AProVE
configuration	standard
runtime (wallclock)	1.69547891617 seconds
cpu usage	3.64933727
max memory	2.2673408E8

stage attributes

key	value
output-size	1838
starexec-result	YES

output

/export/starexec/sandbox2/solver/bin/starexec_run_standard /export/starexec/sandbox2/benchmark/theBenchmark.xml /export/starexec/sandbox2/output/output_files -------------------------------------------------------------------------------- YES proof of /export/starexec/sandbox2/benchmark/theBenchmark.xml # AProVE Commit ID: 794c25de1cacf0d048858bcd21c9a779e1221865 marcel 20200619 unpublished dirty Quasi decreasingness of the given CTRS could be proven: (0) CTRS (1) CTRSToQTRSProof [SOUND, 0 ms] (2) QTRS (3) QTRSRRRProof [EQUIVALENT, 0 ms] (4) QTRS (5) RisEmptyProof [EQUIVALENT, 0 ms] (6) YES ---------------------------------------- (0) Obligation: Conditional term rewrite system: The TRS R is empty. The conditional TRS C consists of the following conditional rules: f(x) -> a <= x -> b ---------------------------------------- (1) CTRSToQTRSProof (SOUND) The conditional rules have been transormed into unconditional rules according to [CTRS,AAECCNOC]. ---------------------------------------- (2) Obligation: Q restricted rewrite system: The TRS R consists of the following rules: f(x) -> U1(x) U1(b) -> a Q is empty. ---------------------------------------- (3) QTRSRRRProof (EQUIVALENT) Used ordering: Knuth-Bendix order [KBO] with precedence:f_1 > U1_1 > a > b and weight map: b=1 a=2 f_1=1 U1_1=1 The variable weight is 1With this ordering the following rules can be removed by the rule removal processor [LPAR04] because they are oriented strictly: f(x) -> U1(x) U1(b) -> a ---------------------------------------- (4) Obligation: Q restricted rewrite system: R is empty. Q is empty. ---------------------------------------- (5) RisEmptyProof (EQUIVALENT) The TRS R is empty. Hence, termination is trivially proven. ---------------------------------------- (6) YES popout

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job log

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actions

all output return to TRS Conditional