details

property	value
status	complete
benchmark	MYNAT_nosorts-noand_FR.xml
ran by	Akihisa Yamada
cpu timeout	1200 seconds
wallclock timeout	300 seconds
memory limit	137438953472 bytes
execution host	n137.star.cs.uiowa.edu
space	Transformed_CSR_04

run statistics

property	value
solver	muterm 6.0.3
configuration	default
runtime (wallclock)	0.145136833191 seconds
cpu usage	0.064816873
max memory	3760128.0

stage attributes

key	value
output-size	7970
starexec-result	YES

output

/export/starexec/sandbox/solver/bin/starexec_run_default /export/starexec/sandbox/benchmark/theBenchmark.xml /export/starexec/sandbox/output/output_files -------------------------------------------------------------------------------- YES Problem 1: (VAR v_NonEmpty:S M:S N:S X:S) (RULES U11(tt,M:S,N:S) -> U12(tt,activate(M:S),activate(N:S)) U12(tt,M:S,N:S) -> s(plus(activate(N:S),activate(M:S))) U21(tt,M:S,N:S) -> U22(tt,activate(M:S),activate(N:S)) U22(tt,M:S,N:S) -> plus(x(activate(N:S),activate(M:S)),activate(N:S)) activate(X:S) -> X:S plus(N:S,0) -> N:S plus(N:S,s(M:S)) -> U11(tt,M:S,N:S) x(N:S,0) -> 0 x(N:S,s(M:S)) -> U21(tt,M:S,N:S) ) Problem 1: Innermost Equivalent Processor: -> Rules: U11(tt,M:S,N:S) -> U12(tt,activate(M:S),activate(N:S)) U12(tt,M:S,N:S) -> s(plus(activate(N:S),activate(M:S))) U21(tt,M:S,N:S) -> U22(tt,activate(M:S),activate(N:S)) U22(tt,M:S,N:S) -> plus(x(activate(N:S),activate(M:S)),activate(N:S)) activate(X:S) -> X:S plus(N:S,0) -> N:S plus(N:S,s(M:S)) -> U11(tt,M:S,N:S) x(N:S,0) -> 0 x(N:S,s(M:S)) -> U21(tt,M:S,N:S) -> The term rewriting system is non-overlaping or locally confluent overlay system. Therefore, innermost termination implies termination. Problem 1: Dependency Pairs Processor: -> Pairs: U11#(tt,M:S,N:S) -> U12#(tt,activate(M:S),activate(N:S)) U11#(tt,M:S,N:S) -> ACTIVATE(M:S) U11#(tt,M:S,N:S) -> ACTIVATE(N:S) U12#(tt,M:S,N:S) -> ACTIVATE(M:S) U12#(tt,M:S,N:S) -> ACTIVATE(N:S) U12#(tt,M:S,N:S) -> PLUS(activate(N:S),activate(M:S)) U21#(tt,M:S,N:S) -> U22#(tt,activate(M:S),activate(N:S)) U21#(tt,M:S,N:S) -> ACTIVATE(M:S) U21#(tt,M:S,N:S) -> ACTIVATE(N:S) U22#(tt,M:S,N:S) -> ACTIVATE(M:S) U22#(tt,M:S,N:S) -> ACTIVATE(N:S) U22#(tt,M:S,N:S) -> PLUS(x(activate(N:S),activate(M:S)),activate(N:S)) U22#(tt,M:S,N:S) -> X(activate(N:S),activate(M:S)) PLUS(N:S,s(M:S)) -> U11#(tt,M:S,N:S) X(N:S,s(M:S)) -> U21#(tt,M:S,N:S) -> Rules: U11(tt,M:S,N:S) -> U12(tt,activate(M:S),activate(N:S)) U12(tt,M:S,N:S) -> s(plus(activate(N:S),activate(M:S))) U21(tt,M:S,N:S) -> U22(tt,activate(M:S),activate(N:S)) U22(tt,M:S,N:S) -> plus(x(activate(N:S),activate(M:S)),activate(N:S)) activate(X:S) -> X:S plus(N:S,0) -> N:S plus(N:S,s(M:S)) -> U11(tt,M:S,N:S) x(N:S,0) -> 0 x(N:S,s(M:S)) -> U21(tt,M:S,N:S) Problem 1: SCC Processor: -> Pairs: U11#(tt,M:S,N:S) -> U12#(tt,activate(M:S),activate(N:S)) U11#(tt,M:S,N:S) -> ACTIVATE(M:S) U11#(tt,M:S,N:S) -> ACTIVATE(N:S) U12#(tt,M:S,N:S) -> ACTIVATE(M:S) U12#(tt,M:S,N:S) -> ACTIVATE(N:S) U12#(tt,M:S,N:S) -> PLUS(activate(N:S),activate(M:S)) U21#(tt,M:S,N:S) -> U22#(tt,activate(M:S),activate(N:S)) U21#(tt,M:S,N:S) -> ACTIVATE(M:S) U21#(tt,M:S,N:S) -> ACTIVATE(N:S) U22#(tt,M:S,N:S) -> ACTIVATE(M:S) U22#(tt,M:S,N:S) -> ACTIVATE(N:S) U22#(tt,M:S,N:S) -> PLUS(x(activate(N:S),activate(M:S)),activate(N:S)) U22#(tt,M:S,N:S) -> X(activate(N:S),activate(M:S)) PLUS(N:S,s(M:S)) -> U11#(tt,M:S,N:S) X(N:S,s(M:S)) -> U21#(tt,M:S,N:S) -> Rules: U11(tt,M:S,N:S) -> U12(tt,activate(M:S),activate(N:S)) U12(tt,M:S,N:S) -> s(plus(activate(N:S),activate(M:S))) U21(tt,M:S,N:S) -> U22(tt,activate(M:S),activate(N:S)) U22(tt,M:S,N:S) -> plus(x(activate(N:S),activate(M:S)),activate(N:S)) activate(X:S) -> X:S plus(N:S,0) -> N:S plus(N:S,s(M:S)) -> U11(tt,M:S,N:S) x(N:S,0) -> 0 x(N:S,s(M:S)) -> U21(tt,M:S,N:S) ->Strongly Connected Components: ->->Cycle: popout

output may be truncated. 'popout' for the full output.

job log

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actions

all output return to TRS Standard