details

property	value
status	complete
benchmark	#3.7.xml
ran by	Akihisa Yamada
cpu timeout	1200 seconds
wallclock timeout	300 seconds
memory limit	137438953472 bytes
execution host	n007.star.cs.uiowa.edu
space	AG01

run statistics

property	value
solver	AProVE21
configuration	standard
runtime (wallclock)	2.13282799721 seconds
cpu usage	5.564268181
max memory	4.8740352E8

stage attributes

key	value
output-size	2468
starexec-result	YES

output

/export/starexec/sandbox/solver/bin/starexec_run_standard /export/starexec/sandbox/benchmark/theBenchmark.xml /export/starexec/sandbox/output/output_files -------------------------------------------------------------------------------- YES proof of /export/starexec/sandbox/benchmark/theBenchmark.xml # AProVE Commit ID: c69e44bd14796315568835c1ffa2502984884775 mhark 20210624 unpublished Termination w.r.t. Q of the given QTRS could be proven: (0) QTRS (1) QTRS Reverse [EQUIVALENT, 0 ms] (2) QTRS (3) RFCMatchBoundsTRSProof [EQUIVALENT, 0 ms] (4) YES ---------------------------------------- (0) Obligation: Q restricted rewrite system: The TRS R consists of the following rules: half(0) -> 0 half(s(s(x))) -> s(half(x)) log(s(0)) -> 0 log(s(s(x))) -> s(log(s(half(x)))) Q is empty. ---------------------------------------- (1) QTRS Reverse (EQUIVALENT) We applied the QTRS Reverse Processor [REVERSE]. ---------------------------------------- (2) Obligation: Q restricted rewrite system: The TRS R consists of the following rules: 0'(half(x)) -> 0'(x) s(s(half(x))) -> half(s(x)) 0'(s(log(x))) -> 0'(x) s(s(log(x))) -> half(s(log(s(x)))) Q is empty. ---------------------------------------- (3) RFCMatchBoundsTRSProof (EQUIVALENT) Termination of the TRS R could be shown with a Match Bound [MATCHBOUNDS1,MATCHBOUNDS2] of 1. This implies Q-termination of R. The following rules were used to construct the certificate: 0'(half(x)) -> 0'(x) s(s(half(x))) -> half(s(x)) 0'(s(log(x))) -> 0'(x) s(s(log(x))) -> half(s(log(s(x)))) The certificate found is represented by the following graph. The certificate consists of the following enumerated nodes: 23, 24, 37, 38, 39, 40, 41, 42, 43, 44 Node 23 is start node and node 24 is final node. Those nodes are connected through the following edges: * 23 to 24 labelled 0'_1(0), 0'_1(1)* 23 to 37 labelled half_1(0)* 23 to 38 labelled half_1(0)* 24 to 24 labelled #_1(0)* 37 to 24 labelled s_1(0)* 37 to 41 labelled half_1(1)* 37 to 42 labelled half_1(1)* 38 to 39 labelled s_1(0)* 39 to 40 labelled log_1(0)* 40 to 24 labelled s_1(0)* 40 to 41 labelled half_1(1)* 40 to 42 labelled half_1(1)* 41 to 24 labelled s_1(1)* 41 to 41 labelled half_1(1)* 41 to 42 labelled half_1(1)* 42 to 43 labelled s_1(1)* 43 to 44 labelled log_1(1)* 44 to 24 labelled s_1(1)* 44 to 41 labelled half_1(1)* 44 to 42 labelled half_1(1) ---------------------------------------- (4) YES popout

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job log

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all output return to TRS Standard