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SRS Standard pair #516968751
details
property
value
status
complete
benchmark
z100.xml
ran by
Akihisa Yamada
cpu timeout
1200 seconds
wallclock timeout
300 seconds
memory limit
137438953472 bytes
execution host
n058.star.cs.uiowa.edu
space
Zantema_04
run statistics
property
value
solver
matchbox-2021-06-18b
configuration
tc21-9.sh
runtime (wallclock)
20.011603117 seconds
cpu usage
56.187785814
max memory
1.688809472E9
stage attributes
key
value
output-size
31974
starexec-result
YES
output
/export/starexec/sandbox2/solver/bin/starexec_run_tc21-9.sh /export/starexec/sandbox2/benchmark/theBenchmark.xml /export/starexec/sandbox2/output/output_files -------------------------------------------------------------------------------- YES ************************************************** summary ************************************************** SRS with 9 rules on 6 letters mirror SRS with 9 rules on 6 letters DP SRS with 18 strict rules and 9 weak rules on 10 letters weights SRS with 4 strict rules and 9 weak rules on 9 letters EDG 3 sub-proofs 1 SRS with 1 rules on 2 letters Usable SRS with 1 rules on 2 letters weights SRS with 0 rules on 0 letters no strict rules 2 SRS with 1 rules on 2 letters Usable SRS with 1 rules on 2 letters weights SRS with 0 rules on 0 letters no strict rules 3 SRS with 2 strict rules and 9 weak rules on 7 letters Matrix { monotone = Weak, domain = Natural, shape = Full, bits = 3, encoding = Ersatz_Binary, dim = 4, solver = Minisatapi, verbose = True, tracing = False} SRS with 1 strict rules and 9 weak rules on 7 letters EDG SRS with 1 strict rules and 9 weak rules on 7 letters Matrix { monotone = Weak, domain = Arctic, shape = Full, bits = 3, encoding = FBV, dim = 2, solver = Minisatapi, verbose = False, tracing = False} SRS with 0 strict rules and 9 weak rules on 6 letters EDG ************************************************** proof ************************************************** property Termination has value Just True for SRS [r1, a] -> [a, a, a, r1] {- Input 0 -} [r2, a] -> [a, a, a, r2] {- Input 1 -} [a, l1] -> [l1, a, a, a] {- Input 2 -} [a, a, l2] -> [l2, a, a] {- Input 3 -} [r1, b] -> [l1, b] {- Input 4 -} [r2, b] -> [l2, a, b] {- Input 5 -} [b, l1] -> [b, r2] {- Input 6 -} [b, l2] -> [b, r1] {- Input 7 -} [a, a] -> [] {- Input 8 -} reason mirror property Termination has value Just True for SRS [a, r1] -> [r1, a, a, a] {- Mirror (Input 0) -} [a, r2] -> [r2, a, a, a] {- Mirror (Input 1) -} [l1, a] -> [a, a, a, l1] {- Mirror (Input 2) -} [l2, a, a] -> [a, a, l2] {- Mirror (Input 3) -} [b, r1] -> [b, l1] {- Mirror (Input 4) -} [b, r2] -> [b, a, l2] {- Mirror (Input 5) -} [l1, b] -> [r2, b] {- Mirror (Input 6) -} [l2, b] -> [r1, b] {- Mirror (Input 7) -} [a, a] -> [] {- Mirror (Input 8) -} reason DP property Termination has value Just True for SRS [a, r1] ->= [r1, a, a, a] {- DP Nontop (Mirror (Input 0)) -} [a, r2] ->= [r2, a, a, a] {- DP Nontop (Mirror (Input 1)) -} [l1, a] ->= [a, a, a, l1] {- DP Nontop (Mirror (Input 2)) -} [l2, a, a] ->= [a, a, l2] {- DP Nontop (Mirror (Input 3)) -} [b, r1] ->= [b, l1] {- DP Nontop (Mirror (Input 4)) -} [b, r2] ->= [b, a, l2] {- DP Nontop (Mirror (Input 5)) -} [l1, b] ->= [r2, b] {- DP Nontop (Mirror (Input 6)) -} [l2, b] ->= [r1, b] {- DP Nontop (Mirror (Input 7)) -} [a, a] ->= [] {- DP Nontop (Mirror (Input 8)) -} [a#, r1] |-> [a#] {- DP (Top 3) (Mirror (Input 0)) -} [a#, r1] |-> [a#, a] {- DP (Top 2) (Mirror (Input 0)) -} [a#, r1] |-> [a#, a, a] {- DP (Top 1) (Mirror (Input 0)) -} [a#, r2] |-> [a#] {- DP (Top 3) (Mirror (Input 1)) -} [a#, r2] |-> [a#, a] {- DP (Top 2) (Mirror (Input 1)) -} [a#, r2] |-> [a#, a, a] {- DP (Top 1) (Mirror (Input 1)) -} [l1#, a] |-> [a#, a, a, l1] {- DP (Top 0) (Mirror (Input 2)) -} [l1#, a] |-> [a#, a, l1] {- DP (Top 1) (Mirror (Input 2)) -} [l1#, a] |-> [a#, l1] {- DP (Top 2) (Mirror (Input 2)) -} [l1#, a] |-> [l1#] {- DP (Top 3) (Mirror (Input 2)) -} [l2#, a, a] |-> [a#, a, l2] {- DP (Top 0) (Mirror (Input 3)) -} [l2#, a, a] |-> [a#, l2] {- DP (Top 1) (Mirror (Input 3)) -} [l2#, a, a] |-> [l2#] {- DP (Top 2) (Mirror (Input 3)) -} [b#, r1] |-> [l1#] {- DP (Top 1) (Mirror (Input 4)) -} [b#, r1] |-> [b#, l1] {- DP (Top 0) (Mirror (Input 4)) -} [b#, r2] |-> [a#, l2] {- DP (Top 1) (Mirror (Input 5)) -} [b#, r2] |-> [l2#] {- DP (Top 2) (Mirror (Input 5)) -} [b#, r2] |-> [b#, a, l2] {- DP (Top 0) (Mirror (Input 5)) -} reason (r1, 1/4) (r2, 1/4) (l1, 1/4) (l2, 1/4) (l1#, 15/8) (l2#, 5/4) (b#, 21/8) property Termination has value Just True for SRS
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