details

property	value
status	complete
benchmark	z072.xml
ran by	Akihisa Yamada
cpu timeout	1200 seconds
wallclock timeout	300 seconds
memory limit	137438953472 bytes
execution host	n004.star.cs.uiowa.edu
space	Zantema_04

run statistics

property	value
solver	AProVE21
configuration	standard
runtime (wallclock)	2.11414289474 seconds
cpu usage	5.275934862
max memory	4.76475392E8

stage attributes

key	value
output-size	2523
starexec-result	YES

output

/export/starexec/sandbox/solver/bin/starexec_run_standard /export/starexec/sandbox/benchmark/theBenchmark.xml /export/starexec/sandbox/output/output_files -------------------------------------------------------------------------------- YES proof of /export/starexec/sandbox/benchmark/theBenchmark.xml # AProVE Commit ID: c69e44bd14796315568835c1ffa2502984884775 mhark 20210624 unpublished Termination w.r.t. Q of the given QTRS could be proven: (0) QTRS (1) RFCMatchBoundsTRSProof [EQUIVALENT, 0 ms] (2) YES ---------------------------------------- (0) Obligation: Q restricted rewrite system: The TRS R consists of the following rules: a(l(x1)) -> l(a(x1)) r(a(a(x1))) -> a(a(r(x1))) b(l(x1)) -> b(a(r(x1))) r(b(x1)) -> l(b(x1)) Q is empty. ---------------------------------------- (1) RFCMatchBoundsTRSProof (EQUIVALENT) Termination of the TRS R could be shown with a Match Bound [MATCHBOUNDS1,MATCHBOUNDS2] of 3. This implies Q-termination of R. The following rules were used to construct the certificate: a(l(x1)) -> l(a(x1)) r(a(a(x1))) -> a(a(r(x1))) b(l(x1)) -> b(a(r(x1))) r(b(x1)) -> l(b(x1)) The certificate found is represented by the following graph. The certificate consists of the following enumerated nodes: 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19 Node 1 is start node and node 2 is final node. Those nodes are connected through the following edges: * 1 to 3 labelled l_1(0)* 1 to 4 labelled a_1(0), b_1(0)* 1 to 11 labelled l_1(1)* 1 to 12 labelled b_1(1)* 2 to 2 labelled #_1(0)* 3 to 2 labelled a_1(0), b_1(0)* 3 to 6 labelled l_1(1)* 3 to 7 labelled b_1(1)* 3 to 15 labelled b_1(2)* 4 to 5 labelled a_1(0)* 4 to 10 labelled l_1(1)* 5 to 2 labelled r_1(0)* 5 to 7 labelled a_1(1)* 5 to 9 labelled l_1(1)* 5 to 17 labelled l_1(2)* 6 to 2 labelled a_1(1)* 6 to 6 labelled l_1(1)* 7 to 8 labelled a_1(1)* 7 to 14 labelled l_1(2)* 8 to 2 labelled r_1(1)* 8 to 7 labelled a_1(1)* 8 to 9 labelled l_1(1)* 8 to 17 labelled l_1(2)* 9 to 2 labelled b_1(1)* 9 to 7 labelled b_1(1)* 9 to 15 labelled b_1(2)* 10 to 9 labelled a_1(1)* 10 to 17 labelled a_1(1)* 11 to 10 labelled a_1(1)* 12 to 13 labelled a_1(1)* 13 to 10 labelled r_1(1)* 13 to 15 labelled a_1(2)* 14 to 9 labelled a_1(2)* 14 to 17 labelled a_1(2)* 15 to 16 labelled a_1(2)* 16 to 14 labelled r_1(2)* 16 to 18 labelled a_1(3)* 17 to 14 labelled a_1(2)* 18 to 19 labelled a_1(3)* 19 to 14 labelled r_1(3)* 19 to 18 labelled a_1(3) ---------------------------------------- (2) YES popout

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