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SRS Standard pair #516969081
details
property
value
status
complete
benchmark
jw4.xml
ran by
Akihisa Yamada
cpu timeout
1200 seconds
wallclock timeout
300 seconds
memory limit
137438953472 bytes
execution host
n112.star.cs.uiowa.edu
space
Waldmann_06_SRS
run statistics
property
value
solver
matchbox-2021-06-18b
configuration
tc21-9.sh
runtime (wallclock)
44.451362133 seconds
cpu usage
137.038504406
max memory
2.618073088E9
stage attributes
key
value
output-size
146701
starexec-result
YES
output
/export/starexec/sandbox2/solver/bin/starexec_run_tc21-9.sh /export/starexec/sandbox2/benchmark/theBenchmark.xml /export/starexec/sandbox2/output/output_files -------------------------------------------------------------------------------- YES ************************************************** summary ************************************************** SRS with 3 rules on 2 letters mirror SRS with 3 rules on 2 letters DP SRS with 9 strict rules and 3 weak rules on 3 letters EDG SRS with 4 strict rules and 3 weak rules on 3 letters Matrix { monotone = Weak, domain = Arctic, shape = Full, bits = 3, encoding = FBV, dim = 4, solver = Minisatapi, verbose = False, tracing = False} SRS with 3 strict rules and 3 weak rules on 3 letters EDG SRS with 3 strict rules and 3 weak rules on 3 letters Matrix { monotone = Weak, domain = Natural, shape = Full, bits = 3, encoding = Ersatz_Binary, dim = 4, solver = Minisatapi, verbose = True, tracing = False} SRS with 2 strict rules and 3 weak rules on 3 letters EDG SRS with 2 strict rules and 3 weak rules on 3 letters Matrix { monotone = Weak, domain = Natural, shape = Full, bits = 3, encoding = Ersatz_Binary, dim = 4, solver = Minisatapi, verbose = True, tracing = False} SRS with 0 strict rules and 3 weak rules on 2 letters EDG ************************************************** proof ************************************************** property Termination has value Just True for SRS [b, a, b, b] -> [b, b, b, a, b] {- Input 0 -} [b, a, a, b, b] -> [b, a, b, b, a, a, b] {- Input 1 -} [b, a, a, a, b, b] -> [b, a, a, b, b, a, a, a, b] {- Input 2 -} reason mirror property Termination has value Just True for SRS [b, b, a, b] -> [b, a, b, b, b] {- Mirror (Input 0) -} [b, b, a, a, b] -> [b, a, a, b, b, a, b] {- Mirror (Input 1) -} [b, b, a, a, a, b] -> [b, a, a, a, b, b, a, a, b] {- Mirror (Input 2) -} reason DP property Termination has value Just True for SRS [b, b, a, b] ->= [b, a, b, b, b] {- DP Nontop (Mirror (Input 0)) -} [b, b, a, a, b] ->= [b, a, a, b, b, a, b] {- DP Nontop (Mirror (Input 1)) -} [b, b, a, a, a, b] ->= [ b , a , a , a , b , b , a , a , b ] {- DP Nontop (Mirror (Input 2)) -} [b#, b, a, b] |-> [b#, b] {- DP (Top 3) (Mirror (Input 0)) -} [b#, b, a, b] |-> [b#, b, b] {- DP (Top 2) (Mirror (Input 0)) -} [b#, b, a, b] |-> [b#, a, b, b, b] {- DP (Top 0) (Mirror (Input 0)) -} [b#, b, a, a, b] |-> [b#, b, a, b] {- DP (Top 3) (Mirror (Input 1)) -} [b#, b, a, a, b] |-> [b#, a, b] {- DP (Top 4) (Mirror (Input 1)) -} [b#, b, a, a, b] |-> [b#, a, a, b, b, a, b] {- DP (Top 0) (Mirror (Input 1)) -} [b#, b, a, a, a, b] |-> [b#, b, a, a, b] {- DP (Top 4) (Mirror (Input 2)) -} [b#, b, a, a, a, b] |-> [b#, a, a, b] {- DP (Top 5) (Mirror (Input 2)) -} [b#, b, a, a, a, b] |-> [ b# , a , a , a , b , b , a , a , b ] {- DP (Top 0) (Mirror (Input 2)) -} reason EDG property Termination has value Just True for SRS [b#, b, a, b] |-> [b#, b] {- DP (Top 3) (Mirror (Input 0)) -} [b#, b, a, a, a, b] |-> [b#, b, a, a, b] {- DP (Top 4) (Mirror (Input 2)) -} [b#, b, a, a, b] |-> [b#, b, a, b] {- DP (Top 3) (Mirror (Input 1)) -} [b#, b, a, b] |-> [b#, b, b] {- DP (Top 2) (Mirror (Input 0)) -} [b, b, a, b] ->= [b, a, b, b, b] {- DP Nontop (Mirror (Input 0)) -} [b, b, a, a, b] ->= [b, a, a, b, b, a, b] {- DP Nontop (Mirror (Input 1)) -} [b, b, a, a, a, b] ->= [ b , a , a , a , b , b , a , a , b ] {- DP Nontop (Mirror (Input 2)) -} reason ( b , Wk / 0A 0A 0A 0A \ | -4A -4A -4A -4A | | -4A -4A -4A -4A | \ -4A -4A -4A -4A / ) ( a , Wk / 0A 0A 4A 4A \ | 0A 0A 0A 4A | | -4A 0A 0A 0A | \ -4A -4A 0A 0A / ) ( b# , Wk / 29A 29A 29A 29A \ | 29A 29A 29A 29A | | 29A 29A 29A 29A | \ 29A 29A 29A 29A / ) property Termination has value Just True for SRS [b#, b, a, b] |-> [b#, b] {- DP (Top 3) (Mirror (Input 0)) -} [b#, b, a, a, b] |-> [b#, b, a, b] {- DP (Top 3) (Mirror (Input 1)) -} [b#, b, a, b] |-> [b#, b, b] {- DP (Top 2) (Mirror (Input 0)) -} [b, b, a, b] ->= [b, a, b, b, b] {- DP Nontop (Mirror (Input 0)) -} [b, b, a, a, b] ->= [b, a, a, b, b, a, b] {- DP Nontop (Mirror (Input 1)) -} [b, b, a, a, a, b] ->= [ b , a , a , a , b , b , a , a , b ] {- DP Nontop (Mirror (Input 2)) -} reason EDG property Termination has value Just True for SRS [b#, b, a, b] |-> [b#, b] {- DP (Top 3) (Mirror (Input 0)) -} [b#, b, a, b] |-> [b#, b, b] {- DP (Top 2) (Mirror (Input 0)) -} [b#, b, a, a, b] |-> [b#, b, a, b] {- DP (Top 3) (Mirror (Input 1)) -} [b, b, a, b] ->= [b, a, b, b, b] {- DP Nontop (Mirror (Input 0)) -}
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