details

property	value
status	complete
benchmark	size-12-alpha-3-num-273.xml
ran by	Akihisa Yamada
cpu timeout	1200 seconds
wallclock timeout	300 seconds
memory limit	137438953472 bytes
execution host	n141.star.cs.uiowa.edu
space	Waldmann_07_size12

run statistics

property	value
solver	ttt2-1.20
configuration	ttt2
runtime (wallclock)	11.5311319828 seconds
cpu usage	42.797832162
max memory	7.03123456E8

stage attributes

key	value
output-size	32278
starexec-result	YES

output

/export/starexec/sandbox/solver/bin/starexec_run_ttt2 /export/starexec/sandbox/benchmark/theBenchmark.xml /export/starexec/sandbox/output/output_files -------------------------------------------------------------------------------- YES Problem: a(x1) -> x1 a(b(x1)) -> c(a(a(c(x1)))) b(x1) -> x1 c(c(x1)) -> b(b(x1)) Proof: DP Processor: DPs: a#(b(x1)) -> c#(x1) a#(b(x1)) -> a#(c(x1)) a#(b(x1)) -> a#(a(c(x1))) a#(b(x1)) -> c#(a(a(c(x1)))) c#(c(x1)) -> b#(x1) c#(c(x1)) -> b#(b(x1)) TRS: a(x1) -> x1 a(b(x1)) -> c(a(a(c(x1)))) b(x1) -> x1 c(c(x1)) -> b(b(x1)) TDG Processor: DPs: a#(b(x1)) -> c#(x1) a#(b(x1)) -> a#(c(x1)) a#(b(x1)) -> a#(a(c(x1))) a#(b(x1)) -> c#(a(a(c(x1)))) c#(c(x1)) -> b#(x1) c#(c(x1)) -> b#(b(x1)) TRS: a(x1) -> x1 a(b(x1)) -> c(a(a(c(x1)))) b(x1) -> x1 c(c(x1)) -> b(b(x1)) graph: a#(b(x1)) -> c#(a(a(c(x1)))) -> c#(c(x1)) -> b#(b(x1)) a#(b(x1)) -> c#(a(a(c(x1)))) -> c#(c(x1)) -> b#(x1) a#(b(x1)) -> c#(x1) -> c#(c(x1)) -> b#(b(x1)) a#(b(x1)) -> c#(x1) -> c#(c(x1)) -> b#(x1) a#(b(x1)) -> a#(c(x1)) -> a#(b(x1)) -> c#(a(a(c(x1)))) a#(b(x1)) -> a#(c(x1)) -> a#(b(x1)) -> a#(a(c(x1))) a#(b(x1)) -> a#(c(x1)) -> a#(b(x1)) -> a#(c(x1)) a#(b(x1)) -> a#(c(x1)) -> a#(b(x1)) -> c#(x1) a#(b(x1)) -> a#(a(c(x1))) -> a#(b(x1)) -> c#(a(a(c(x1)))) a#(b(x1)) -> a#(a(c(x1))) -> a#(b(x1)) -> a#(a(c(x1))) a#(b(x1)) -> a#(a(c(x1))) -> a#(b(x1)) -> a#(c(x1)) a#(b(x1)) -> a#(a(c(x1))) -> a#(b(x1)) -> c#(x1) SCC Processor: #sccs: 1 #rules: 2 #arcs: 12/36 DPs: a#(b(x1)) -> a#(c(x1)) a#(b(x1)) -> a#(a(c(x1))) TRS: a(x1) -> x1 a(b(x1)) -> c(a(a(c(x1)))) b(x1) -> x1 c(c(x1)) -> b(b(x1)) Root-Labeling Processor: DPs: a{#,(f6)}(f6(b)(b(f6)(x1))) -> a{#,(f6)}(f6(c)(c(f6)(x1))) a{#,(f6)}(f6(b)(b(a)(x1))) -> a{#,(f6)}(f6(c)(c(a)(x1))) a{#,(f6)}(f6(b)(b(b)(x1))) -> a{#,(f6)}(f6(c)(c(b)(x1))) a{#,(f6)}(f6(b)(b(c)(x1))) -> a{#,(f6)}(f6(c)(c(c)(x1))) a{#,(f6)}(f6(b)(b(f6)(x1))) -> a{#,(f6)}(f6(a)(a(c)(c(f6)(x1)))) a{#,(f6)}(f6(b)(b(a)(x1))) -> a{#,(f6)}(f6(a)(a(c)(c(a)(x1)))) a{#,(f6)}(f6(b)(b(b)(x1))) -> a{#,(f6)}(f6(a)(a(c)(c(b)(x1)))) a{#,(f6)}(f6(b)(b(c)(x1))) -> a{#,(f6)}(f6(a)(a(c)(c(c)(x1)))) TRS: f6(a)(a(f6)(x1)) -> f6(f6)(x1) f6(a)(a(a)(x1)) -> f6(a)(x1) f6(a)(a(b)(x1)) -> f6(b)(x1) f6(a)(a(c)(x1)) -> f6(c)(x1) a(a)(a(f6)(x1)) -> a(f6)(x1) a(a)(a(a)(x1)) -> a(a)(x1) a(a)(a(b)(x1)) -> a(b)(x1) a(a)(a(c)(x1)) -> a(c)(x1) b(a)(a(f6)(x1)) -> b(f6)(x1) b(a)(a(a)(x1)) -> b(a)(x1) b(a)(a(b)(x1)) -> b(b)(x1) b(a)(a(c)(x1)) -> b(c)(x1) c(a)(a(f6)(x1)) -> c(f6)(x1) c(a)(a(a)(x1)) -> c(a)(x1) c(a)(a(b)(x1)) -> c(b)(x1) c(a)(a(c)(x1)) -> c(c)(x1) f6(a)(a(b)(b(f6)(x1))) -> f6(c)(c(a)(a(a)(a(c)(c(f6)(x1))))) f6(a)(a(b)(b(a)(x1))) -> f6(c)(c(a)(a(a)(a(c)(c(a)(x1))))) f6(a)(a(b)(b(b)(x1))) -> f6(c)(c(a)(a(a)(a(c)(c(b)(x1))))) f6(a)(a(b)(b(c)(x1))) -> f6(c)(c(a)(a(a)(a(c)(c(c)(x1))))) a(a)(a(b)(b(f6)(x1))) -> a(c)(c(a)(a(a)(a(c)(c(f6)(x1))))) a(a)(a(b)(b(a)(x1))) -> a(c)(c(a)(a(a)(a(c)(c(a)(x1))))) a(a)(a(b)(b(b)(x1))) -> a(c)(c(a)(a(a)(a(c)(c(b)(x1))))) popout

output may be truncated. 'popout' for the full output.

job log

popout

actions

all output return to SRS Standard