details

property	value
status	complete
benchmark	un17.xml
ran by	Akihisa Yamada
cpu timeout	1200 seconds
wallclock timeout	300 seconds
memory limit	137438953472 bytes
execution host	n170.star.cs.uiowa.edu
space	Trafo_06

run statistics

property	value
solver	matchbox-2021-06-18b
configuration	tc21-9.sh
runtime (wallclock)	233.601127148 seconds
cpu usage	683.445273312
max memory	9.24637184E9

stage attributes

key	value
output-size	202972
starexec-result	YES

output

/export/starexec/sandbox2/solver/bin/starexec_run_tc21-9.sh /export/starexec/sandbox2/benchmark/theBenchmark.xml /export/starexec/sandbox2/output/output_files -------------------------------------------------------------------------------- YES ************************************************** summary ************************************************** SRS with 3 rules on 2 letters mirror SRS with 3 rules on 2 letters DP SRS with 8 strict rules and 3 weak rules on 3 letters EDG SRS with 8 strict rules and 3 weak rules on 3 letters Matrix { monotone = Weak, domain = Natural, shape = Full, bits = 3, encoding = Ersatz_Binary, dim = 4, solver = Minisatapi, verbose = True, tracing = False} SRS with 5 strict rules and 3 weak rules on 3 letters EDG SRS with 5 strict rules and 3 weak rules on 3 letters Matrix { monotone = Weak, domain = Natural, shape = Full, bits = 3, encoding = Ersatz_Binary, dim = 4, solver = Minisatapi, verbose = True, tracing = False} SRS with 3 strict rules and 3 weak rules on 3 letters EDG SRS with 3 strict rules and 3 weak rules on 3 letters Matrix { monotone = Weak, domain = Arctic, shape = Full, bits = 2, encoding = Ersatz_Binary, dim = 8, solver = Minisatapi, verbose = True, tracing = False} SRS with 1 strict rules and 3 weak rules on 3 letters EDG ************************************************** proof ************************************************** property Termination has value Just True for SRS [b, b, b] -> [b, b, a, b, a, b, a, b] {- Input 0 -} [b, a, b, b] -> [b, a, b, a, b, a, a, b] {- Input 1 -} [b, b, a, b, a, b, a, a, b] -> [b, b, b, b, a, b] {- Input 2 -} reason mirror property Termination has value Just True for SRS [b, b, b] -> [b, a, b, a, b, a, b, b] {- Mirror (Input 0) -} [b, b, a, b] -> [b, a, a, b, a, b, a, b] {- Mirror (Input 1) -} [b, a, a, b, a, b, a, b, b] -> [b, a, b, b, b, b] {- Mirror (Input 2) -} reason DP property Termination has value Just True for SRS [b, b, b] ->= [b, a, b, a, b, a, b, b] {- DP Nontop (Mirror (Input 0)) -} [b, b, a, b] ->= [b, a, a, b, a, b, a, b] {- DP Nontop (Mirror (Input 1)) -} [b, a, a, b, a, b, a, b, b] ->= [ b , a , b , b , b , b ] {- DP Nontop (Mirror (Input 2)) -} [b#, b, b] |-> [b#, a, b, b] {- DP (Top 4) (Mirror (Input 0)) -} [b#, b, b] |-> [b#, a, b, a, b, b] {- DP (Top 2) (Mirror (Input 0)) -} [b#, b, b] |-> [b#, a, b, a, b, a, b, b] {- DP (Top 0) (Mirror (Input 0)) -} [b#, b, a, b] |-> [b#, a, b, a, b] {- DP (Top 3) (Mirror (Input 1)) -} [b#, b, a, b] |-> [b#, a, a, b, a, b, a, b] {- DP (Top 0) (Mirror (Input 1)) -} [b#, a, a, b, a, b, a, b, b] |-> [b#, b, b] {- DP (Top 3) (Mirror (Input 2)) -} [b#, a, a, b, a, b, a, b, b] |-> [ b# , b , b , b ] {- DP (Top 2) (Mirror (Input 2)) -} [b#, a, a, b, a, b, a, b, b] |-> [ b# , a , b , b , b , b ] {- DP (Top 0) (Mirror (Input 2)) -} reason EDG property Termination has value Just True for SRS [b#, b, b] |-> [b#, a, b, b] {- DP (Top 4) (Mirror (Input 0)) -} [b#, a, a, b, a, b, a, b, b] |-> [ b# , a , b , b , b , b ] {- DP (Top 0) (Mirror (Input 2)) -} [b#, a, a, b, a, b, a, b, b] |-> [ b# , b , b , b ] {- DP (Top 2) (Mirror (Input 2)) -} [b#, a, a, b, a, b, a, b, b] |-> [b#, b, b] {- DP (Top 3) (Mirror (Input 2)) -} [b#, b, a, b] |-> [b#, a, a, b, a, b, a, b] {- DP (Top 0) (Mirror (Input 1)) -} [b#, b, a, b] |-> [b#, a, b, a, b] {- DP (Top 3) (Mirror (Input 1)) -} [b#, b, b] |-> [b#, a, b, a, b, a, b, b] {- DP (Top 0) (Mirror (Input 0)) -} [b#, b, b] |-> [b#, a, b, a, b, b] {- DP (Top 2) (Mirror (Input 0)) -} [b, b, b] ->= [b, a, b, a, b, a, b, b] {- DP Nontop (Mirror (Input 0)) -} [b, b, a, b] ->= [b, a, a, b, a, b, a, b] {- DP Nontop (Mirror (Input 1)) -} [b, a, a, b, a, b, a, b, b] ->= [ b , a , b , b , b , b ] {- DP Nontop (Mirror (Input 2)) -} reason ( b , Wk / 0 0 1 0 \ | 0 0 0 1 | | 0 0 0 1 | \ 0 0 0 1 / ) ( a , Wk / 1 1 0 0 \ | 1 0 0 0 | | 0 0 0 0 | \ 0 0 0 1 / ) ( b# , Wk / 0 1 0 5 \ | 0 0 0 0 | | 0 0 0 0 | \ 0 0 0 1 / ) property Termination has value Just True for SRS [b#, b, b] |-> [b#, a, b, b] {- DP (Top 4) (Mirror (Input 0)) -} [b#, a, a, b, a, b, a, b, b] |-> [ b# , a , b , b , b , b ] {- DP (Top 0) (Mirror (Input 2)) -} [b#, a, a, b, a, b, a, b, b] |-> [ b# , b , b , b ] {- DP (Top 2) (Mirror (Input 2)) -} [b#, a, a, b, a, b, a, b, b] |-> [b#, b, b] {- DP (Top 3) (Mirror (Input 2)) -} [b#, b, a, b] |-> [b#, a, a, b, a, b, a, b] {- DP (Top 0) (Mirror (Input 1)) -} [b, b, b] ->= [b, a, b, a, b, a, b, b] {- DP Nontop (Mirror (Input 0)) -} [b, b, a, b] ->= [b, a, a, b, a, b, a, b] {- DP Nontop (Mirror (Input 1)) -} [b, a, a, b, a, b, a, b, b] ->= [ b , a , b , b , b , b ] {- DP Nontop (Mirror (Input 2)) -} reason EDG property Termination has value Just True popout

output may be truncated. 'popout' for the full output.

job log

popout

actions

all output return to SRS Standard