details

property	value
status	complete
benchmark	un06.xml
ran by	Akihisa Yamada
cpu timeout	1200 seconds
wallclock timeout	300 seconds
memory limit	137438953472 bytes
execution host	n167.star.cs.uiowa.edu
space	Trafo_06

run statistics

property	value
solver	matchbox-2021-06-18b
configuration	tc21-9.sh
runtime (wallclock)	37.5827970505 seconds
cpu usage	94.068495361
max memory	2.504167424E9

stage attributes

key	value
output-size	100257
starexec-result	YES

output

/export/starexec/sandbox2/solver/bin/starexec_run_tc21-9.sh /export/starexec/sandbox2/benchmark/theBenchmark.xml /export/starexec/sandbox2/output/output_files -------------------------------------------------------------------------------- YES ************************************************** summary ************************************************** SRS with 4 rules on 2 letters DP SRS with 8 strict rules and 4 weak rules on 3 letters EDG SRS with 8 strict rules and 4 weak rules on 3 letters Matrix { monotone = Weak, domain = Arctic, shape = Full, bits = 16, encoding = Ersatz_Binary, dim = 2, solver = Minisatapi, verbose = True, tracing = False} SRS with 7 strict rules and 4 weak rules on 3 letters EDG 2 sub-proofs 1 SRS with 1 strict rules and 4 weak rules on 3 letters Matrix { monotone = Weak, domain = Natural, shape = Full, bits = 3, encoding = Ersatz_Binary, dim = 4, solver = Minisatapi, verbose = True, tracing = False} SRS with 0 strict rules and 4 weak rules on 2 letters EDG 2 SRS with 2 strict rules and 4 weak rules on 3 letters Matrix { monotone = Weak, domain = Natural, shape = Full, bits = 3, encoding = Ersatz_Binary, dim = 4, solver = Minisatapi, verbose = True, tracing = False} SRS with 0 strict rules and 4 weak rules on 2 letters EDG ************************************************** proof ************************************************** property Termination has value Just True for SRS [b, b] -> [b, a, b, a, a, b] {- Input 0 -} [b, b, a, b] -> [b, a, b, b] {- Input 1 -} [b, a, a, a, b, a, a, b] -> [b, a, a, a, b, b] {- Input 2 -} [b, b, a, a, b] -> [b, a, a, b, b] {- Input 3 -} reason DP property Termination has value Just True for SRS [b, b] ->= [b, a, b, a, a, b] {- DP Nontop (Input 0) -} [b, b, a, b] ->= [b, a, b, b] {- DP Nontop (Input 1) -} [b, a, a, a, b, a, a, b] ->= [b, a, a, a, b, b] {- DP Nontop (Input 2) -} [b, b, a, a, b] ->= [b, a, a, b, b] {- DP Nontop (Input 3) -} [b#, b] |-> [b#, a, b, a, a, b] {- DP (Top 0) (Input 0) -} [b#, b] |-> [b#, a, a, b] {- DP (Top 2) (Input 0) -} [b#, b, a, b] |-> [b#, b] {- DP (Top 2) (Input 1) -} [b#, b, a, b] |-> [b#, a, b, b] {- DP (Top 0) (Input 1) -} [b#, b, a, a, b] |-> [b#, b] {- DP (Top 3) (Input 3) -} [b#, b, a, a, b] |-> [b#, a, a, b, b] {- DP (Top 0) (Input 3) -} [b#, a, a, a, b, a, a, b] |-> [b#, b] {- DP (Top 4) (Input 2) -} [b#, a, a, a, b, a, a, b] |-> [b#, a, a, a, b, b] {- DP (Top 0) (Input 2) -} reason EDG property Termination has value Just True for SRS [b#, b] |-> [b#, a, b, a, a, b] {- DP (Top 0) (Input 0) -} [b#, a, a, a, b, a, a, b] |-> [b#, a, a, a, b, b] {- DP (Top 0) (Input 2) -} [b#, a, a, a, b, a, a, b] |-> [b#, b] {- DP (Top 4) (Input 2) -} [b#, b, a, a, b] |-> [b#, a, a, b, b] {- DP (Top 0) (Input 3) -} [b#, b, a, a, b] |-> [b#, b] {- DP (Top 3) (Input 3) -} [b#, b, a, b] |-> [b#, a, b, b] {- DP (Top 0) (Input 1) -} [b#, b, a, b] |-> [b#, b] {- DP (Top 2) (Input 1) -} [b#, b] |-> [b#, a, a, b] {- DP (Top 2) (Input 0) -} [b, b] ->= [b, a, b, a, a, b] {- DP Nontop (Input 0) -} [b, b, a, b] ->= [b, a, b, b] {- DP Nontop (Input 1) -} [b, a, a, a, b, a, a, b] ->= [b, a, a, a, b, b] {- DP Nontop (Input 2) -} [b, b, a, a, b] ->= [b, a, a, b, b] {- DP Nontop (Input 3) -} reason ( b , Wk / - 0A \ \ - 0A / ) ( a , Wk / 1A 1A \ \ - 0A / ) ( b# , Wk / 9A 11A \ \ - 0A / ) property Termination has value Just True for SRS [b#, b] |-> [b#, a, b, a, a, b] {- DP (Top 0) (Input 0) -} [b#, a, a, a, b, a, a, b] |-> [b#, a, a, a, b, b] {- DP (Top 0) (Input 2) -} [b#, b, a, a, b] |-> [b#, a, a, b, b] {- DP (Top 0) (Input 3) -} [b#, b, a, a, b] |-> [b#, b] {- DP (Top 3) (Input 3) -} [b#, b, a, b] |-> [b#, a, b, b] {- DP (Top 0) (Input 1) -} [b#, b, a, b] |-> [b#, b] {- DP (Top 2) (Input 1) -} [b#, b] |-> [b#, a, a, b] {- DP (Top 2) (Input 0) -} [b, b] ->= [b, a, b, a, a, b] {- DP Nontop (Input 0) -} [b, b, a, b] ->= [b, a, b, b] {- DP Nontop (Input 1) -} [b, a, a, a, b, a, a, b] ->= [b, a, a, a, b, b] {- DP Nontop (Input 2) -} [b, b, a, a, b] ->= [b, a, a, b, b] {- DP Nontop (Input 3) -} reason EDG property Termination has value Just True for SRS [b#, a, a, a, b, a, a, b] |-> [b#, a, a, a, b, b] {- DP (Top 0) (Input 2) -} [b, b] ->= [b, a, b, a, a, b] {- DP Nontop (Input 0) -} [b, b, a, b] ->= [b, a, b, b] {- DP Nontop (Input 1) -} [b, a, a, a, b, a, a, b] ->= [b, a, a, a, b, b] {- DP Nontop (Input 2) -} [b, b, a, a, b] ->= [b, a, a, b, b] {- DP Nontop (Input 3) -} reason popout

output may be truncated. 'popout' for the full output.

job log

popout

actions

all output return to SRS Standard