details

property	value
status	complete
benchmark	random-230.xml
ran by	Akihisa Yamada
cpu timeout	1200 seconds
wallclock timeout	300 seconds
memory limit	137438953472 bytes
execution host	n009.star.cs.uiowa.edu
space	Waldmann_19

run statistics

property	value
solver	matchbox-2021-06-18b
configuration	tc21-9.sh
runtime (wallclock)	3.0541510582 seconds
cpu usage	7.596221224
max memory	4.6147584E8

stage attributes

key	value
output-size	16808
starexec-result	YES

output

/export/starexec/sandbox/solver/bin/starexec_run_tc21-9.sh /export/starexec/sandbox/benchmark/theBenchmark.xml /export/starexec/sandbox/output/output_files -------------------------------------------------------------------------------- YES ************************************************** summary ************************************************** SRS with 3 rules on 2 letters mirror SRS with 3 rules on 2 letters DP SRS with 9 strict rules and 3 weak rules on 4 letters weights SRS with 2 strict rules and 3 weak rules on 4 letters EDG 2 sub-proofs 1 SRS with 1 strict rules and 3 weak rules on 3 letters remove some, by Config { method = Overlap,width = 4,unlabel = True} SRS with 0 strict rules and 3 weak rules on 2 letters no strict rules 2 SRS with 1 strict rules and 3 weak rules on 3 letters remove some, by Config { method = Overlap,width = 4,unlabel = True} SRS with 0 strict rules and 3 weak rules on 2 letters no strict rules ************************************************** proof ************************************************** property Termination has value Just True for SRS [b, b, b, b] -> [b, b, b, a] {- Input 0 -} [a, b, a, a] -> [b, a, b, a] {- Input 1 -} [b, a, a, b] -> [a, b, a, b] {- Input 2 -} reason mirror property Termination has value Just True for SRS [b, b, b, b] -> [a, b, b, b] {- Mirror (Input 0) -} [a, a, b, a] -> [a, b, a, b] {- Mirror (Input 1) -} [b, a, a, b] -> [b, a, b, a] {- Mirror (Input 2) -} reason DP property Termination has value Just True for SRS [b, b, b, b] ->= [a, b, b, b] {- DP Nontop (Mirror (Input 0)) -} [a, a, b, a] ->= [a, b, a, b] {- DP Nontop (Mirror (Input 1)) -} [b, a, a, b] ->= [b, a, b, a] {- DP Nontop (Mirror (Input 2)) -} [b#, b, b, b] |-> [a#, b, b, b] {- DP (Top 0) (Mirror (Input 0)) -} [b#, a, a, b] |-> [b#, a] {- DP (Top 2) (Mirror (Input 2)) -} [b#, a, a, b] |-> [b#, a, b, a] {- DP (Top 0) (Mirror (Input 2)) -} [b#, a, a, b] |-> [a#] {- DP (Top 3) (Mirror (Input 2)) -} [b#, a, a, b] |-> [a#, b, a] {- DP (Top 1) (Mirror (Input 2)) -} [a#, a, b, a] |-> [b#] {- DP (Top 3) (Mirror (Input 1)) -} [a#, a, b, a] |-> [b#, a, b] {- DP (Top 1) (Mirror (Input 1)) -} [a#, a, b, a] |-> [a#, b] {- DP (Top 2) (Mirror (Input 1)) -} [a#, a, b, a] |-> [a#, b, a, b] {- DP (Top 0) (Mirror (Input 1)) -} reason (b, 2/1) (a, 2/1) (b#, 1/1) property Termination has value Just True for SRS [b, b, b, b] ->= [a, b, b, b] {- DP Nontop (Mirror (Input 0)) -} [a, a, b, a] ->= [a, b, a, b] {- DP Nontop (Mirror (Input 1)) -} [b, a, a, b] ->= [b, a, b, a] {- DP Nontop (Mirror (Input 2)) -} [b#, a, a, b] |-> [b#, a, b, a] {- DP (Top 0) (Mirror (Input 2)) -} [a#, a, b, a] |-> [a#, b, a, b] {- DP (Top 0) (Mirror (Input 1)) -} reason EDG property Termination has value Just True for SRS [b#, a, a, b] |-> [b#, a, b, a] {- DP (Top 0) (Mirror (Input 2)) -} [b, b, b, b] ->= [a, b, b, b] {- DP Nontop (Mirror (Input 0)) -} [a, a, b, a] ->= [a, b, a, b] {- DP Nontop (Mirror (Input 1)) -} [b, a, a, b] ->= [b, a, b, a] {- DP Nontop (Mirror (Input 2)) -} reason Tiling { method = Overlap, width = 4, state_type = Bit64, map_type = Enum, unlabel = True, print_completion_steps = False, print_tiles = False, max_num_tiles = Just 1000, max_num_rules = Just 100000, verbose = False, tracing = False} steps 2 using 39 tiles remove some unmatched rules steps: 2 property Termination has value Just True for SRS [b, b, b, b] ->= [a, b, b, b] {- DP Nontop (Mirror (Input 0)) -} [a, a, b, a] ->= [a, b, a, b] {- DP Nontop (Mirror (Input 1)) -} [b, a, a, b] ->= [b, a, b, a] {- DP Nontop (Mirror (Input 2)) -} reason no strict rules property Termination has value Just True for SRS [a#, a, b, a] |-> [a#, b, a, b] {- DP (Top 0) (Mirror (Input 1)) -} [b, b, b, b] ->= [a, b, b, b] {- DP Nontop (Mirror (Input 0)) -} [a, a, b, a] ->= [a, b, a, b] {- DP Nontop (Mirror (Input 1)) -} [b, a, a, b] ->= [b, a, b, a] {- DP Nontop (Mirror (Input 2)) -} reason popout

output may be truncated. 'popout' for the full output.

job log

popout

actions

all output return to SRS Standard