details

property	value
status	complete
benchmark	abaababa-aabababaab.srs.xml
ran by	Akihisa Yamada
cpu timeout	1200 seconds
wallclock timeout	300 seconds
memory limit	137438953472 bytes
execution host	n026.star.cs.uiowa.edu
space	Wenzel_16

run statistics

property	value
solver	matchbox-2021-06-18b
configuration	tc21-9.sh
runtime (wallclock)	128.862949848 seconds
cpu usage	458.348996119
max memory	3.375357952E9

stage attributes

key	value
output-size	120919
starexec-result	YES

output

/export/starexec/sandbox/solver/bin/starexec_run_tc21-9.sh /export/starexec/sandbox/benchmark/theBenchmark.xml /export/starexec/sandbox/output/output_files -------------------------------------------------------------------------------- YES ************************************************** summary ************************************************** SRS with 1 rules on 2 letters mirror SRS with 1 rules on 2 letters DP SRS with 5 strict rules and 1 weak rules on 3 letters EDG SRS with 5 strict rules and 1 weak rules on 3 letters Matrix { monotone = Weak, domain = Arctic, shape = Full, bits = 3, encoding = FBV, dim = 6, solver = Minisatapi, verbose = False, tracing = False} SRS with 4 strict rules and 1 weak rules on 3 letters EDG SRS with 4 strict rules and 1 weak rules on 3 letters Matrix { monotone = Weak, domain = Arctic, shape = Full, bits = 4, encoding = Ersatz_Binary, dim = 6, solver = Minisatapi, verbose = True, tracing = False} SRS with 2 strict rules and 1 weak rules on 3 letters EDG SRS with 2 strict rules and 1 weak rules on 3 letters Matrix { monotone = Weak, domain = Natural, shape = Full, bits = 3, encoding = Ersatz_Binary, dim = 4, solver = Minisatapi, verbose = True, tracing = False} SRS with 0 strict rules and 1 weak rules on 2 letters EDG ************************************************** proof ************************************************** property Termination has value Just True for SRS [a, b, a, a, b, a, b, a] -> [a, a, b, a, b, a, b, a, a, b] {- Input 0 -} reason mirror property Termination has value Just True for SRS [a, b, a, b, a, a, b, a] -> [ b , a , a , b , a , b , a , b , a , a ] {- Mirror (Input 0) -} reason DP property Termination has value Just True for SRS [a, b, a, b, a, a, b, a] ->= [ b , a , a , b , a , b , a , b , a , a ] {- DP Nontop (Mirror (Input 0)) -} [a#, b, a, b, a, a, b, a] |-> [a#, a] {- DP (Top 8) (Mirror (Input 0)) -} [a#, b, a, b, a, a, b, a] |-> [ a# , a , b , a , b , a , b , a , a ] {- DP (Top 1) (Mirror (Input 0)) -} [a#, b, a, b, a, a, b, a] |-> [a#, b, a, a] {- DP (Top 6) (Mirror (Input 0)) -} [a#, b, a, b, a, a, b, a] |-> [ a# , b , a , b , a , a ] {- DP (Top 4) (Mirror (Input 0)) -} [a#, b, a, b, a, a, b, a] |-> [ a# , b , a , b , a , b , a , a ] {- DP (Top 2) (Mirror (Input 0)) -} reason EDG property Termination has value Just True for SRS [a#, b, a, b, a, a, b, a] |-> [a#, a] {- DP (Top 8) (Mirror (Input 0)) -} [a#, b, a, b, a, a, b, a] |-> [ a# , b , a , b , a , b , a , a ] {- DP (Top 2) (Mirror (Input 0)) -} [a#, b, a, b, a, a, b, a] |-> [ a# , b , a , b , a , a ] {- DP (Top 4) (Mirror (Input 0)) -} [a#, b, a, b, a, a, b, a] |-> [a#, b, a, a] {- DP (Top 6) (Mirror (Input 0)) -} [a#, b, a, b, a, a, b, a] |-> [ a# , a , b , a , b , a , b , a , a ] {- DP (Top 1) (Mirror (Input 0)) -} [a, b, a, b, a, a, b, a] ->= [ b , a , a , b , a , b , a , b , a , a ] {- DP Nontop (Mirror (Input 0)) -} reason ( a , Wk / 0A 0A 0A 0A 0A 0A \ | 0A 0A 0A 0A 0A 0A | | 0A 0A 0A 0A 0A 0A | | 0A 0A 0A 0A 0A 0A | | -6A -6A 0A 0A 0A 0A | \ -6A -6A -6A 0A 0A 0A / ) ( b , Wk / 0A 0A 0A 0A 0A 0A \ | -6A -6A -6A -6A 0A 0A | | -6A -6A -6A -6A -6A 0A | | -6A -6A -6A -6A -6A -6A | | -6A -6A -6A -6A -6A -6A | \ -6A -6A -6A -6A -6A -6A / ) ( a# , Wk / 1A 2A 2A 2A 2A 2A \ | 1A 2A 2A 2A 2A 2A | | 1A 2A 2A 2A 2A 2A | | 1A 2A 2A 2A 2A 2A | | 1A 2A 2A 2A 2A 2A | \ 1A 2A 2A 2A 2A 2A / ) property Termination has value Just True for SRS [a#, b, a, b, a, a, b, a] |-> [a#, a] {- DP (Top 8) (Mirror (Input 0)) -} [a#, b, a, b, a, a, b, a] |-> [ a# , b , a , b , a , a ] {- DP (Top 4) (Mirror (Input 0)) -} [a#, b, a, b, a, a, b, a] |-> [a#, b, a, a] {- DP (Top 6) (Mirror (Input 0)) -} [a#, b, a, b, a, a, b, a] |-> [ a# , a , b , a , b , a , b , a , a ] {- DP (Top 1) (Mirror (Input 0)) -} [a, b, a, b, a, a, b, a] ->= [ b , a , a , b , a , b , a , b , a , a ] {- DP Nontop (Mirror (Input 0)) -} reason EDG property Termination has value Just True for SRS [a#, b, a, b, a, a, b, a] |-> [a#, a] {- DP (Top 8) (Mirror (Input 0)) -} [a#, b, a, b, a, a, b, a] |-> [ a# , a , b , a , b , a , b , a , a ] {- DP (Top 1) (Mirror (Input 0)) -} [a#, b, a, b, a, a, b, a] |-> [a#, b, a, a] {- DP (Top 6) (Mirror (Input 0)) -} [a#, b, a, b, a, a, b, a] |-> [ a# , b , a , b , a , a ] {- DP (Top 4) (Mirror (Input 0)) -} [a, b, a, b, a, a, b, a] ->= [ b , a , a , b , a , b , a , b , a , a ] {- DP Nontop (Mirror (Input 0)) -} reason ( a , Wk / - 0A - - - 0A \ | 0A - - 1A 0A 0A | | - - - - 1A - | popout

output may be truncated. 'popout' for the full output.

job log

popout

actions

all output return to SRS Standard