details

property	value
status	complete
benchmark	abbcaabbca-aabbcabbcaabbc.srs.xml
ran by	Akihisa Yamada
cpu timeout	1200 seconds
wallclock timeout	300 seconds
memory limit	137438953472 bytes
execution host	n070.star.cs.uiowa.edu
space	Wenzel_16

run statistics

property	value
solver	matchbox-2021-06-18b
configuration	tc21-9.sh
runtime (wallclock)	77.0319709778 seconds
cpu usage	281.255170472
max memory	2.978492416E9

stage attributes

key	value
output-size	121814
starexec-result	YES

output

/export/starexec/sandbox2/solver/bin/starexec_run_tc21-9.sh /export/starexec/sandbox2/benchmark/theBenchmark.xml /export/starexec/sandbox2/output/output_files -------------------------------------------------------------------------------- YES ************************************************** summary ************************************************** SRS with 1 rules on 3 letters mirror SRS with 1 rules on 3 letters DP SRS with 4 strict rules and 1 weak rules on 4 letters EDG SRS with 4 strict rules and 1 weak rules on 4 letters Matrix { monotone = Weak, domain = Arctic, shape = Full, bits = 3, encoding = FBV, dim = 4, solver = Minisatapi, verbose = False, tracing = False} SRS with 3 strict rules and 1 weak rules on 4 letters EDG SRS with 3 strict rules and 1 weak rules on 4 letters Matrix { monotone = Weak, domain = Arctic, shape = Full, bits = 4, encoding = Ersatz_Binary, dim = 6, solver = Minisatapi, verbose = True, tracing = False} SRS with 2 strict rules and 1 weak rules on 4 letters EDG SRS with 2 strict rules and 1 weak rules on 4 letters Matrix { monotone = Weak, domain = Natural, shape = Full, bits = 3, encoding = Ersatz_Binary, dim = 4, solver = Minisatapi, verbose = True, tracing = False} SRS with 0 strict rules and 1 weak rules on 3 letters EDG ************************************************** proof ************************************************** property Termination has value Just True for SRS [a, b, b, c, a, a, b, b, c, a] -> [ a , a , b , b , c , a , b , b , c , a , a , b , b , c ] {- Input 0 -} reason mirror property Termination has value Just True for SRS [a, c, b, b, a, a, c, b, b, a] -> [ c , b , b , a , a , c , b , b , a , c , b , b , a , a ] {- Mirror (Input 0) -} reason DP property Termination has value Just True for SRS [a, c, b, b, a, a, c, b, b, a] ->= [ c , b , b , a , a , c , b , b , a , c , b , b , a , a ] {- DP Nontop (Mirror (Input 0)) -} [a#, c, b, b, a, a, c, b, b, a] |-> [a#, a] {- DP (Top 12) (Mirror (Input 0)) -} [a#, c, b, b, a, a, c, b, b, a] |-> [ a# , a , c , b , b , a , c , b , b , a , a ] {- DP (Top 3) (Mirror (Input 0)) -} [a#, c, b, b, a, a, c, b, b, a] |-> [ a# , c , b , b , a , a ] {- DP (Top 8) (Mirror (Input 0)) -} [a#, c, b, b, a, a, c, b, b, a] |-> [ a# , c , b , b , a , c , b , b , a , a ] {- DP (Top 4) (Mirror (Input 0)) -} reason EDG property Termination has value Just True for SRS [a#, c, b, b, a, a, c, b, b, a] |-> [a#, a] {- DP (Top 12) (Mirror (Input 0)) -} [a#, c, b, b, a, a, c, b, b, a] |-> [ a# , c , b , b , a , c , b , b , a , a ] {- DP (Top 4) (Mirror (Input 0)) -} [a#, c, b, b, a, a, c, b, b, a] |-> [ a# , c , b , b , a , a ] {- DP (Top 8) (Mirror (Input 0)) -} [a#, c, b, b, a, a, c, b, b, a] |-> [ a# , a , c , b , b , a , c , b , b , a , a ] {- DP (Top 3) (Mirror (Input 0)) -} [a, c, b, b, a, a, c, b, b, a] ->= [ c , b , b , a , a , c , b , b , a , c , b , b , a , a ] {- DP Nontop (Mirror (Input 0)) -} reason ( a , Wk / 0A 0A 0A 0A \ | 0A 0A 0A 0A | | 0A 0A 0A 0A | \ -4A -4A 0A 0A / ) ( c , Wk / 0A 0A 0A 0A \ | -4A 0A 0A 0A | | -4A -4A -4A -4A | \ -4A -4A -4A -4A / ) ( b , Wk / 0A 0A 0A 0A \ | -4A -4A 0A 0A | | -4A -4A -4A 0A | \ -4A -4A -4A -4A / ) ( a# , Wk / 21A 22A 22A 22A \ | 21A 22A 22A 22A | | 21A 22A 22A 22A | \ 21A 22A 22A 22A / ) property Termination has value Just True for SRS [a#, c, b, b, a, a, c, b, b, a] |-> [a#, a] {- DP (Top 12) (Mirror (Input 0)) -} [a#, c, b, b, a, a, c, b, b, a] |-> [ a# , c , b , b , a , a ] {- DP (Top 8) (Mirror (Input 0)) -} [a#, c, b, b, a, a, c, b, b, a] |-> [ a# , a , c , b , b , a , c , b , b , a , a ] {- DP (Top 3) (Mirror (Input 0)) -} [a, c, b, b, a, a, c, b, b, a] ->= [ c , b , b , a , a , c , b , b , a , c , b , b , a , a ] {- DP Nontop (Mirror (Input 0)) -} reason EDG property Termination has value Just True for SRS [a#, c, b, b, a, a, c, b, b, a] |-> [a#, a] {- DP (Top 12) (Mirror (Input 0)) -} [a#, c, b, b, a, a, c, b, b, a] |-> [ a# , a , c , b , b , a , c , b , b , a , a ] {- DP (Top 3) (Mirror (Input 0)) -} [a#, c, b, b, a, a, c, b, b, a] |-> [ a# , c , b , b , a , a ] {- DP (Top 8) (Mirror (Input 0)) -} [a, c, b, b, a, a, c, b, b, a] ->= [ c , b , b , a , a , c , b , b , a , c , b , b , a , a ] {- DP Nontop (Mirror (Input 0)) -} reason ( a , Wk / - 0A 0A 1A 0A 1A \ | - - 0A 1A 1A 0A | | 0A 1A - - 0A 0A | | - - 0A 1A - - | | 0A 1A - 2A - 2A | \ - - - - - 0A / ) ( c , Wk / - - 0A - - 3A \ popout

output may be truncated. 'popout' for the full output.

job log

popout

actions

all output return to SRS Standard