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SRS Standard pair #516977985
details
property
value
status
complete
benchmark
abcbaabcba-aabcbabcbaabcb.srs.xml
ran by
Akihisa Yamada
cpu timeout
1200 seconds
wallclock timeout
300 seconds
memory limit
137438953472 bytes
execution host
n074.star.cs.uiowa.edu
space
Wenzel_16
run statistics
property
value
solver
matchbox-2021-06-18b
configuration
tc21-9.sh
runtime (wallclock)
77.1354799271 seconds
cpu usage
289.790585784
max memory
2.847813632E9
stage attributes
key
value
output-size
114762
starexec-result
YES
output
/export/starexec/sandbox2/solver/bin/starexec_run_tc21-9.sh /export/starexec/sandbox2/benchmark/theBenchmark.xml /export/starexec/sandbox2/output/output_files -------------------------------------------------------------------------------- YES ************************************************** summary ************************************************** SRS with 1 rules on 3 letters mirror SRS with 1 rules on 3 letters DP SRS with 4 strict rules and 1 weak rules on 4 letters EDG SRS with 4 strict rules and 1 weak rules on 4 letters Matrix { monotone = Weak, domain = Arctic, shape = Full, bits = 3, encoding = FBV, dim = 4, solver = Minisatapi, verbose = False, tracing = False} SRS with 3 strict rules and 1 weak rules on 4 letters EDG SRS with 3 strict rules and 1 weak rules on 4 letters Matrix { monotone = Weak, domain = Arctic, shape = Full, bits = 4, encoding = Ersatz_Binary, dim = 6, solver = Minisatapi, verbose = True, tracing = False} SRS with 2 strict rules and 1 weak rules on 4 letters EDG SRS with 2 strict rules and 1 weak rules on 4 letters Matrix { monotone = Weak, domain = Natural, shape = Full, bits = 3, encoding = Ersatz_Binary, dim = 4, solver = Minisatapi, verbose = True, tracing = False} SRS with 0 strict rules and 1 weak rules on 3 letters EDG ************************************************** proof ************************************************** property Termination has value Just True for SRS [a, b, c, b, a, a, b, c, b, a] -> [ a , a , b , c , b , a , b , c , b , a , a , b , c , b ] {- Input 0 -} reason mirror property Termination has value Just True for SRS [a, b, c, b, a, a, b, c, b, a] -> [ b , c , b , a , a , b , c , b , a , b , c , b , a , a ] {- Mirror (Input 0) -} reason DP property Termination has value Just True for SRS [a, b, c, b, a, a, b, c, b, a] ->= [ b , c , b , a , a , b , c , b , a , b , c , b , a , a ] {- DP Nontop (Mirror (Input 0)) -} [a#, b, c, b, a, a, b, c, b, a] |-> [a#, a] {- DP (Top 12) (Mirror (Input 0)) -} [a#, b, c, b, a, a, b, c, b, a] |-> [ a# , a , b , c , b , a , b , c , b , a , a ] {- DP (Top 3) (Mirror (Input 0)) -} [a#, b, c, b, a, a, b, c, b, a] |-> [ a# , b , c , b , a , a ] {- DP (Top 8) (Mirror (Input 0)) -} [a#, b, c, b, a, a, b, c, b, a] |-> [ a# , b , c , b , a , b , c , b , a , a ] {- DP (Top 4) (Mirror (Input 0)) -} reason EDG property Termination has value Just True for SRS [a#, b, c, b, a, a, b, c, b, a] |-> [a#, a] {- DP (Top 12) (Mirror (Input 0)) -} [a#, b, c, b, a, a, b, c, b, a] |-> [ a# , b , c , b , a , b , c , b , a , a ] {- DP (Top 4) (Mirror (Input 0)) -} [a#, b, c, b, a, a, b, c, b, a] |-> [ a# , b , c , b , a , a ] {- DP (Top 8) (Mirror (Input 0)) -} [a#, b, c, b, a, a, b, c, b, a] |-> [ a# , a , b , c , b , a , b , c , b , a , a ] {- DP (Top 3) (Mirror (Input 0)) -} [a, b, c, b, a, a, b, c, b, a] ->= [ b , c , b , a , a , b , c , b , a , b , c , b , a , a ] {- DP Nontop (Mirror (Input 0)) -} reason ( a , Wk / 0A 0A 0A 0A \ | 0A 0A 0A 0A | | 0A 0A 0A 0A | \ -4A -4A 0A 0A / ) ( b , Wk / 0A 0A 0A 0A \ | -4A -4A 0A 0A | | -4A -4A -4A 0A | \ -4A -4A -4A 0A / ) ( c , Wk / 0A 0A 0A 0A \ | -4A 0A 0A 0A | | -4A -4A -4A 0A | \ -4A -4A -4A -4A / ) ( a# , Wk / 24A 25A 25A 25A \ | 24A 25A 25A 25A | | 24A 25A 25A 25A | \ 24A 25A 25A 25A / ) property Termination has value Just True for SRS [a#, b, c, b, a, a, b, c, b, a] |-> [a#, a] {- DP (Top 12) (Mirror (Input 0)) -} [a#, b, c, b, a, a, b, c, b, a] |-> [ a# , b , c , b , a , a ] {- DP (Top 8) (Mirror (Input 0)) -} [a#, b, c, b, a, a, b, c, b, a] |-> [ a# , a , b , c , b , a , b , c , b , a , a ] {- DP (Top 3) (Mirror (Input 0)) -} [a, b, c, b, a, a, b, c, b, a] ->= [ b , c , b , a , a , b , c , b , a , b , c , b , a , a ] {- DP Nontop (Mirror (Input 0)) -} reason EDG property Termination has value Just True for SRS [a#, b, c, b, a, a, b, c, b, a] |-> [a#, a] {- DP (Top 12) (Mirror (Input 0)) -} [a#, b, c, b, a, a, b, c, b, a] |-> [ a# , a , b , c , b , a , b , c , b , a , a ] {- DP (Top 3) (Mirror (Input 0)) -} [a#, b, c, b, a, a, b, c, b, a] |-> [ a# , b , c , b , a , a ] {- DP (Top 8) (Mirror (Input 0)) -} [a, b, c, b, a, a, b, c, b, a] ->= [ b , c , b , a , a , b , c , b , a , b , c , b , a , a ] {- DP Nontop (Mirror (Input 0)) -} reason ( a , Wk / 0A 1A 0A - - 0A \ | - 1A 0A 1A - - | | 0A 1A 1A 2A 0A 1A | | - - 0A 1A - - | | 0A 1A 0A 1A 0A - | \ - - - - - 0A / ) ( b , Wk / 0A - - 0A - - \
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