details

property	value
status	complete
benchmark	343.xml
ran by	Akihisa Yamada
cpu timeout	1200 seconds
wallclock timeout	300 seconds
memory limit	137438953472 bytes
execution host	n028.star.cs.uiowa.edu
space	COPS

run statistics

property	value
solver	AProVE21
configuration	standard
runtime (wallclock)	2.08863210678 seconds
cpu usage	5.349845986
max memory	4.76618752E8

stage attributes

key	value
output-size	1972
starexec-result	YES

output

/export/starexec/sandbox/solver/bin/starexec_run_standard /export/starexec/sandbox/benchmark/theBenchmark.xml /export/starexec/sandbox/output/output_files -------------------------------------------------------------------------------- YES proof of /export/starexec/sandbox/benchmark/theBenchmark.xml # AProVE Commit ID: c69e44bd14796315568835c1ffa2502984884775 mhark 20210624 unpublished Quasi decreasingness of the given CTRS could be proven: (0) CTRS (1) CTRSToQTRSProof [SOUND, 0 ms] (2) QTRS (3) QTRSRRRProof [EQUIVALENT, 27 ms] (4) QTRS (5) RisEmptyProof [EQUIVALENT, 0 ms] (6) YES ---------------------------------------- (0) Obligation: Conditional term rewrite system: The TRS R consists of the following rules: add(x, 0) -> x The conditional TRS C consists of the following conditional rules: add(x, s(y)) -> s(z) <= add(x, y) -> z ---------------------------------------- (1) CTRSToQTRSProof (SOUND) The conditional rules have been transormed into unconditional rules according to [CTRS,AAECCNOC]. ---------------------------------------- (2) Obligation: Q restricted rewrite system: The TRS R consists of the following rules: add(x, s(y)) -> U1(add(x, y)) U1(z) -> s(z) add(x, 0) -> x Q is empty. ---------------------------------------- (3) QTRSRRRProof (EQUIVALENT) Used ordering: Knuth-Bendix order [KBO] with precedence:0 > add_2 > U1_1 > s_1 and weight map: 0=1 s_1=1 U1_1=1 add_2=0 The variable weight is 1With this ordering the following rules can be removed by the rule removal processor [LPAR04] because they are oriented strictly: add(x, s(y)) -> U1(add(x, y)) U1(z) -> s(z) add(x, 0) -> x ---------------------------------------- (4) Obligation: Q restricted rewrite system: R is empty. Q is empty. ---------------------------------------- (5) RisEmptyProof (EQUIVALENT) The TRS R is empty. Hence, termination is trivially proven. ---------------------------------------- (6) YES popout

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job log

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actions

all output return to TRS Conditional