/export/starexec/sandbox/solver/bin/starexec_run_standard /export/starexec/sandbox/benchmark/theBenchmark.xml /export/starexec/sandbox/output/output_files


--------------------------------------------------------------------------------


YES
proof of /export/starexec/sandbox/benchmark/theBenchmark.xml
# AProVE Commit ID: 48fb2092695e11cc9f56e44b17a92a5f88ffb256 marcel 20180622 unpublished dirty


Termination w.r.t. Q of the given QTRS could be proven:

(0) QTRS
(1) QTRS Reverse [EQUIVALENT, 0 ms]
(2) QTRS
(3) RFCMatchBoundsTRSProof [EQUIVALENT, 0 ms]
(4) YES


----------------------------------------

(0)
Obligation:
Q restricted rewrite system:
The TRS R consists of the following rules:

   half(0) -> 0
   half(s(0)) -> 0
   half(s(s(x))) -> s(half(x))
   bits(0) -> 0
   bits(s(x)) -> s(bits(half(s(x))))

Q is empty.

----------------------------------------

(1) QTRS Reverse (EQUIVALENT)
We applied the QTRS Reverse Processor [REVERSE].
----------------------------------------

(2)
Obligation:
Q restricted rewrite system:
The TRS R consists of the following rules:

   0'(half(x)) -> 0'(x)
   0'(s(half(x))) -> 0'(x)
   s(s(half(x))) -> half(s(x))
   0'(bits(x)) -> 0'(x)
   s(bits(x)) -> s(half(bits(s(x))))

Q is empty.

----------------------------------------

(3) RFCMatchBoundsTRSProof (EQUIVALENT)
Termination of the TRS R could be shown with a Match Bound [MATCHBOUNDS1,MATCHBOUNDS2] of 1. This implies Q-termination of R.
The following rules were used to construct the certificate:

   0'(half(x)) -> 0'(x)
   0'(s(half(x))) -> 0'(x)
   s(s(half(x))) -> half(s(x))
   0'(bits(x)) -> 0'(x)
   s(bits(x)) -> s(half(bits(s(x))))

The certificate found is represented by the following graph.
The certificate consists of the following enumerated nodes:
63, 64, 65, 66, 67, 68, 69, 70, 71, 72

Node 63 is start node and node 64 is final node.

Those nodes are connected through the following edges:

* 63 to 64 labelled 0'_1(0), 0'_1(1)* 63 to 65 labelled half_1(0)* 63 to 66 labelled s_1(0)* 64 to 64 labelled #_1(0)* 65 to 64 labelled s_1(0)* 65 to 69 labelled half_1(1)* 65 to 70 labelled s_1(1)* 66 to 67 labelled half_1(0)* 67 to 68 labelled bits_1(0)* 68 to 64 labelled s_1(0)* 68 to 69 labelled half_1(1)* 68 to 70 labelled s_1(1)* 69 to 64 labelled s_1(1)* 69 to 69 labelled half_1(1)* 69 to 70 labelled s_1(1)* 70 to 71 labelled half_1(1)* 71 to 72 labelled bits_1(1)* 72 to 64 labelled s_1(1)* 72 to 69 labelled half_1(1)* 72 to 70 labelled s_1(1)


----------------------------------------

(4)
YES