/export/starexec/sandbox/solver/bin/starexec_run_standard /export/starexec/sandbox/benchmark/theBenchmark.xml /export/starexec/sandbox/output/output_files -------------------------------------------------------------------------------- YES proof of /export/starexec/sandbox/benchmark/theBenchmark.xml # AProVE Commit ID: 48fb2092695e11cc9f56e44b17a92a5f88ffb256 marcel 20180622 unpublished dirty Termination w.r.t. Q of the given QTRS could be proven: (0) QTRS (1) QTRS Reverse [EQUIVALENT, 0 ms] (2) QTRS (3) RFCMatchBoundsTRSProof [EQUIVALENT, 0 ms] (4) YES ---------------------------------------- (0) Obligation: Q restricted rewrite system: The TRS R consists of the following rules: half(0) -> 0 half(s(0)) -> 0 half(s(s(x))) -> s(half(x)) bits(0) -> 0 bits(s(x)) -> s(bits(half(s(x)))) The set Q consists of the following terms: half(0) half(s(0)) half(s(s(x0))) bits(0) bits(s(x0)) ---------------------------------------- (1) QTRS Reverse (EQUIVALENT) We applied the QTRS Reverse Processor [REVERSE]. ---------------------------------------- (2) Obligation: Q restricted rewrite system: The TRS R consists of the following rules: 0'(half(x)) -> 0'(x) 0'(s(half(x))) -> 0'(x) s(s(half(x))) -> half(s(x)) 0'(bits(x)) -> 0'(x) s(bits(x)) -> s(half(bits(s(x)))) Q is empty. ---------------------------------------- (3) RFCMatchBoundsTRSProof (EQUIVALENT) Termination of the TRS R could be shown with a Match Bound [MATCHBOUNDS1,MATCHBOUNDS2] of 1. This implies Q-termination of R. The following rules were used to construct the certificate: 0'(half(x)) -> 0'(x) 0'(s(half(x))) -> 0'(x) s(s(half(x))) -> half(s(x)) 0'(bits(x)) -> 0'(x) s(bits(x)) -> s(half(bits(s(x)))) The certificate found is represented by the following graph. The certificate consists of the following enumerated nodes: 3, 4, 5, 6, 7, 8, 9, 10, 11, 12 Node 3 is start node and node 4 is final node. Those nodes are connected through the following edges: * 3 to 4 labelled 0'_1(0), 0'_1(1)* 3 to 5 labelled half_1(0)* 3 to 6 labelled s_1(0)* 4 to 4 labelled #_1(0)* 5 to 4 labelled s_1(0)* 5 to 9 labelled half_1(1)* 5 to 10 labelled s_1(1)* 6 to 7 labelled half_1(0)* 7 to 8 labelled bits_1(0)* 8 to 4 labelled s_1(0)* 8 to 9 labelled half_1(1)* 8 to 10 labelled s_1(1)* 9 to 4 labelled s_1(1)* 9 to 9 labelled half_1(1)* 9 to 10 labelled s_1(1)* 10 to 11 labelled half_1(1)* 11 to 12 labelled bits_1(1)* 12 to 4 labelled s_1(1)* 12 to 9 labelled half_1(1)* 12 to 10 labelled s_1(1) ---------------------------------------- (4) YES