/export/starexec/sandbox/solver/bin/starexec_run_c /export/starexec/sandbox/benchmark/theBenchmark.c /export/starexec/sandbox/output/output_files -------------------------------------------------------------------------------- YES proof of /export/starexec/sandbox/benchmark/theBenchmark.c # AProVE Commit ID: 48fb2092695e11cc9f56e44b17a92a5f88ffb256 marcel 20180622 unpublished dirty Termination of the given C Problem could be proven: (0) C Problem (1) CToLLVMProof [EQUIVALENT, 178 ms] (2) LLVM problem (3) LLVMToTerminationGraphProof [EQUIVALENT, 3398 ms] (4) LLVM Symbolic Execution Graph (5) SymbolicExecutionGraphToSCCProof [SOUND, 0 ms] (6) LLVM Symbolic Execution SCC (7) SCC2IRS [SOUND, 180 ms] (8) IntTRS (9) IntTRSCompressionProof [EQUIVALENT, 0 ms] (10) IntTRS (11) PolynomialOrderProcessor [EQUIVALENT, 16 ms] (12) YES ---------------------------------------- (0) Obligation: c file /export/starexec/sandbox/benchmark/theBenchmark.c ---------------------------------------- (1) CToLLVMProof (EQUIVALENT) Compiled c-file /export/starexec/sandbox/benchmark/theBenchmark.c to LLVM. ---------------------------------------- (2) Obligation: LLVM Problem Aliases: Data layout: "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" Machine: "x86_64-pc-linux-gnu" Type definitions: Global variables: Function declarations and definitions: *BasicFunctionTypename: "__VERIFIER_nondet_int" returnParam: i32 parameters: () variableLength: false visibilityType: DEFAULT callingConvention: ccc *BasicFunctionTypename: "malloc" returnParam: *i8 parameters: (i64) variableLength: false visibilityType: DEFAULT callingConvention: ccc *BasicFunctionTypename: "__VERIFIER_nondet_String" linkageType: EXTERNALLY_VISIBLE returnParam: *i8 parameters: () variableLength: false visibilityType: DEFAULT callingConvention: ccc 0: %length = alloca i32, align 4 %nondetString = alloca *i8, align 8 %1 = call i32 @__VERIFIER_nondet_int() store %1, %length %2 = load %length %3 = icmp slt %2 1 br %3, %4, %5 4: store 1, %length br %5 5: %6 = load %length %7 = sext i32 %6 to i64 %8 = mul %7 1 %9 = call *i8 @malloc(i64 %8) store %9, %nondetString %10 = load %length %11 = sub %10 1 %12 = sext i32 %11 to i64 %13 = load %nondetString %14 = getelementptr %13, %12 store 0, %14 %15 = load %nondetString ret %15 *BasicFunctionTypename: "cstrncmp" linkageType: EXTERNALLY_VISIBLE returnParam: i32 parameters: (s1 *i8, s2 *i8, n i32) variableLength: false visibilityType: DEFAULT callingConvention: ccc 0: %1 = alloca i32, align 4 %2 = alloca *i8, align 8 %3 = alloca *i8, align 8 %4 = alloca i32, align 4 %uc1 = alloca i8, align 1 %uc2 = alloca i8, align 1 store %s1, %2 store %s2, %3 store %n, %4 %5 = load %4 %6 = icmp eq %5 0 br %6, %7, %8 7: store 0, %1 br %57 8: br %9 9: %10 = load %4 %11 = add %10 -1 store %11, %4 %12 = icmp sgt %10 0 br %12, %13, %21 13: %14 = load %2 %15 = load %14 %16 = sext i8 %15 to i32 %17 = load %3 %18 = load %17 %19 = sext i8 %18 to i32 %20 = icmp eq %16 %19 br %21 21: %22 = phi [0, %9], [%20, %13] br %22, %23, %37 23: %24 = load %4 %25 = icmp eq %24 0 br %25, %31, %26 26: %27 = load %2 %28 = load %27 %29 = sext i8 %28 to i32 %30 = icmp eq %29 0 br %30, %31, %32 31: store 0, %1 br %57 32: %33 = load %2 %34 = getelementptr %33, 1 store %34, %2 %35 = load %3 %36 = getelementptr %35, 1 store %36, %3 br %9 37: %38 = load %2 %39 = load %38 store %39, %uc1 %40 = load %3 %41 = load %40 store %41, %uc2 %42 = load %uc1 %43 = zext i8 %42 to i32 %44 = load %uc2 %45 = zext i8 %44 to i32 %46 = icmp slt %43 %45 br %46, %47, %48 47: br %55 48: %49 = load %uc1 %50 = zext i8 %49 to i32 %51 = load %uc2 %52 = zext i8 %51 to i32 %53 = icmp sgt %50 %52 %54 = zext i1 %53 to i32 br %55 55: %56 = phi [-1, %47], [%54, %48] store %56, %1 br %57 57: %58 = load %1 ret %58 *BasicFunctionTypename: "main" linkageType: EXTERNALLY_VISIBLE returnParam: i32 parameters: () variableLength: false visibilityType: DEFAULT callingConvention: ccc 0: %1 = alloca i32, align 4 store 0, %1 %2 = call *i8 @__VERIFIER_nondet_String() %3 = call *i8 @__VERIFIER_nondet_String() %4 = call i32 @__VERIFIER_nondet_int() %5 = call i32 @cstrncmp(*i8 %2, *i8 %3, i32 %4) ret %5 Analyze Termination of all function calls matching the pattern: main() ---------------------------------------- (3) LLVMToTerminationGraphProof (EQUIVALENT) Constructed symbolic execution graph for LLVM program and proved memory safety. ---------------------------------------- (4) Obligation: SE Graph ---------------------------------------- (5) SymbolicExecutionGraphToSCCProof (SOUND) Splitted symbolic execution graph to 1 SCC. ---------------------------------------- (6) Obligation: SCC ---------------------------------------- (7) SCC2IRS (SOUND) Transformed LLVM symbolic execution graph SCC into a rewrite problem. Log: Generated rules. Obtained 33 rulesP rules: f_620(v989, v990, v991, v992, v993, v994, v995, v996, v997, 0, v1000, 1, v1002, v1003, v1004, v1005, v1006, v1007, v1008, v1009, v1010, v1011, v1012, v1013, v1014, v1015, 3, 7, 2, 4, 8) -> f_621(v989, v990, v991, v992, v993, v994, v995, v996, v997, 0, v1000, v1016, 1, v1002, v1003, v1004, v1005, v1006, v1007, v1008, v1009, v1010, v1011, v1012, v1013, v1014, v1015, 3, 7, 2, 4, 8) :|: 1 + v1016 = v1000 && 0 <= v1016 f_621(v989, v990, v991, v992, v993, v994, v995, v996, v997, 0, v1000, v1016, 1, v1002, v1003, v1004, v1005, v1006, v1007, v1008, v1009, v1010, v1011, v1012, v1013, v1014, v1015, 3, 7, 2, 4, 8) -> f_622(v989, v990, v991, v992, v993, v994, v995, v996, v997, 0, v1000, v1016, 1, v1002, v1003, v1004, v1005, v1006, v1007, v1008, v1009, v1010, v1011, v1012, v1013, v1014, v1015, 3, 7, 2, 4, 8) :|: TRUE f_622(v989, v990, v991, v992, v993, v994, v995, v996, v997, 0, v1000, v1016, 1, v1002, v1003, v1004, v1005, v1006, v1007, v1008, v1009, v1010, v1011, v1012, v1013, v1014, v1015, 3, 7, 2, 4, 8) -> f_623(v989, v990, v991, v992, v993, v994, v995, v996, v997, 0, v1000, v1016, 1, v1002, v1003, v1004, v1005, v1006, v1007, v1008, v1009, v1010, v1011, v1012, v1013, v1014, v1015, 3, 7, 2, 4, 8) :|: 0 = 0 f_623(v989, v990, v991, v992, v993, v994, v995, v996, v997, 0, v1000, v1016, 1, v1002, v1003, v1004, v1005, v1006, v1007, v1008, v1009, v1010, v1011, v1012, v1013, v1014, v1015, 3, 7, 2, 4, 8) -> f_624(v989, v990, v991, v992, v993, v994, v995, v996, v997, 0, v1000, v1016, 1, v1002, v1003, v1004, v1005, v1006, v1007, v1008, v1009, v1010, v1011, v1012, v1013, v1014, v1015, 3, 7, 2, 4, 8) :|: TRUE f_624(v989, v990, v991, v992, v993, v994, v995, v996, v997, 0, v1000, v1016, 1, v1002, v1003, v1004, v1005, v1006, v1007, v1008, v1009, v1010, v1011, v1012, v1013, v1014, v1015, 3, 7, 2, 4, 8) -> f_625(v989, v990, v991, v992, v993, v994, v995, v996, v997, 0, v1000, v1016, 1, v1005, v1003, v1004, v1002, v1006, v1007, v1008, v1009, v1010, v1011, v1012, v1013, v1014, v1015, 3, 7, 2, 4, 8) :|: 0 = 0 f_625(v989, v990, v991, v992, v993, v994, v995, v996, v997, 0, v1000, v1016, 1, v1005, v1003, v1004, v1002, v1006, v1007, v1008, v1009, v1010, v1011, v1012, v1013, v1014, v1015, 3, 7, 2, 4, 8) -> f_626(v989, v990, v991, v992, v993, v994, v995, v996, v997, 0, v1000, v1016, 1, v1005, v1018, v1003, v1004, v1002, v1006, v1007, v1008, v1009, v1010, v1011, v1012, v1013, v1014, v1015, 3, 7, 2, 4, 8) :|: TRUE f_626(v989, v990, v991, v992, v993, v994, v995, v996, v997, 0, v1000, v1016, 1, v1005, v1018, v1003, v1004, v1002, v1006, v1007, v1008, v1009, v1010, v1011, v1012, v1013, v1014, v1015, 3, 7, 2, 4, 8) -> f_627(v989, v990, v991, v992, v993, v994, v995, v996, v997, 0, v1000, v1016, 1, v1005, v1018, v1004, v1003, v1002, v1006, v1007, v1008, v1009, v1010, v1011, v1012, v1013, v1014, v1015, 3, 7, 2, 4, 8) :|: 0 = 0 f_627(v989, v990, v991, v992, v993, v994, v995, v996, v997, 0, v1000, v1016, 1, v1005, v1018, v1004, v1003, v1002, v1006, v1007, v1008, v1009, v1010, v1011, v1012, v1013, v1014, v1015, 3, 7, 2, 4, 8) -> f_628(v989, v990, v991, v992, v993, v994, v995, v996, v997, 0, v1000, v1016, 1, v1005, v1018, v1006, v1003, v1002, v1004, v1007, v1008, v1009, v1010, v1011, v1012, v1013, v1014, v1015, 3, 7, 2, 4, 8) :|: 0 = 0 f_628(v989, v990, v991, v992, v993, v994, v995, v996, v997, 0, v1000, v1016, 1, v1005, v1018, v1006, v1003, v1002, v1004, v1007, v1008, v1009, v1010, v1011, v1012, v1013, v1014, v1015, 3, 7, 2, 4, 8) -> f_629(v989, v990, v991, v992, v993, v994, v995, v996, v997, 0, v1000, v1016, 1, v1005, v1018, v1006, v1020, v1003, v1002, v1004, v1007, v1008, v1009, v1010, v1011, v1012, v1013, v1014, v1015, 3, 7, 2, 4, 8) :|: TRUE f_629(v989, v990, v991, v992, v993, v994, v995, v996, v997, 0, v1000, v1016, 1, v1005, v1018, v1006, v1020, v1003, v1002, v1004, v1007, v1008, v1009, v1010, v1011, v1012, v1013, v1014, v1015, 3, 7, 2, 4, 8) -> f_630(v989, v990, v991, v992, v993, v994, v995, v996, v997, 0, v1000, v1016, 1, v1005, v1018, v1006, v1020, v1002, v1003, v1004, v1007, v1008, v1009, v1010, v1011, v1012, v1013, v1014, v1015, 3, 7, 2, 4, 8) :|: 0 = 0 f_630(v989, v990, v991, v992, v993, v994, v995, v996, v997, 0, v1000, v1016, 1, v1005, v1018, v1006, v1020, v1002, v1003, v1004, v1007, v1008, v1009, v1010, v1011, v1012, v1013, v1014, v1015, 3, 7, 2, 4, 8) -> f_631(v989, v990, v991, v992, v993, v994, v995, v996, v997, 0, v1000, v1016, 1, v1005, v1020, v1006, v1002, v1003, v1004, v1007, v1008, v1009, v1010, v1011, v1012, v1013, v1014, v1015, 3, 7, 2, 4, 8) :|: v1018 = v1020 f_631(v989, v990, v991, v992, v993, v994, v995, v996, v997, 0, v1000, v1016, 1, v1005, v1020, v1006, v1002, v1003, v1004, v1007, v1008, v1009, v1010, v1011, v1012, v1013, v1014, v1015, 3, 7, 2, 4, 8) -> f_633(v989, v990, v991, v992, v993, v994, v995, v996, v997, 0, v1000, v1016, 1, v1005, v1020, v1006, v1002, v1003, v1004, v1007, v1008, v1009, v1010, v1011, v1012, v1013, v1014, v1015, 3, 7, 2, 4, 8) :|: 0 = 0 f_633(v989, v990, v991, v992, v993, v994, v995, v996, v997, 0, v1000, v1016, 1, v1005, v1020, v1006, v1002, v1003, v1004, v1007, v1008, v1009, v1010, v1011, v1012, v1013, v1014, v1015, 3, 7, 2, 4, 8) -> f_635(v989, v990, v991, v992, v993, v994, v995, v996, v997, 0, v1000, v1016, 1, v1005, v1020, v1006, v1002, v1003, v1004, v1007, v1008, v1009, v1010, v1011, v1012, v1013, v1014, v1015, 3, 7, 2, 4, 8) :|: 0 = 0 f_635(v989, v990, v991, v992, v993, v994, v995, v996, v997, 0, v1000, v1016, 1, v1005, v1020, v1006, v1002, v1003, v1004, v1007, v1008, v1009, v1010, v1011, v1012, v1013, v1014, v1015, 3, 7, 2, 4, 8) -> f_637(v989, v990, v991, v992, v993, v994, v995, v996, v997, 0, v1000, v1016, 1, v1005, v1020, v1006, v1002, v1003, v1004, v1007, v1008, v1009, v1010, v1011, v1012, v1013, v1014, v1015, 3, 7, 2, 4, 8) :|: TRUE f_637(v989, v990, v991, v992, v993, v994, v995, v996, v997, 0, v1000, v1016, 1, v1005, v1020, v1006, v1002, v1003, v1004, v1007, v1008, v1009, v1010, v1011, v1012, v1013, v1014, v1015, 3, 7, 2, 4, 8) -> f_639(v989, v990, v991, v992, v993, v994, v995, v996, v997, 0, v1000, v1016, 1, v1005, v1020, v1006, v1002, v1003, v1004, v1007, v1008, v1009, v1010, v1011, v1012, v1013, v1014, v1015, 3, 7, 2, 4, 8) :|: 0 = 0 f_639(v989, v990, v991, v992, v993, v994, v995, v996, v997, 0, v1000, v1016, 1, v1005, v1020, v1006, v1002, v1003, v1004, v1007, v1008, v1009, v1010, v1011, v1012, v1013, v1014, v1015, 3, 7, 2, 4, 8) -> f_642(v989, v990, v991, v992, v993, v994, v995, v996, v997, 0, v1000, v1016, 1, v1005, v1020, v1006, v1002, v1003, v1004, v1007, v1008, v1009, v1010, v1011, v1012, v1013, v1014, v1015, 3, 7, 2, 4, 8) :|: v1016 != 0 && 2 <= v1000 && 3 <= v991 f_642(v989, v990, v991, v992, v993, v994, v995, v996, v997, 0, v1000, v1016, 1, v1005, v1020, v1006, v1002, v1003, v1004, v1007, v1008, v1009, v1010, v1011, v1012, v1013, v1014, v1015, 3, 7, 2, 4, 8) -> f_645(v989, v990, v991, v992, v993, v994, v995, v996, v997, 0, v1000, v1016, 1, v1005, v1020, v1006, v1002, v1003, v1004, v1007, v1008, v1009, v1010, v1011, v1012, v1013, v1014, v1015, 3, 7, 2, 4, 8) :|: 0 = 0 f_645(v989, v990, v991, v992, v993, v994, v995, v996, v997, 0, v1000, v1016, 1, v1005, v1020, v1006, v1002, v1003, v1004, v1007, v1008, v1009, v1010, v1011, v1012, v1013, v1014, v1015, 3, 7, 2, 4, 8) -> f_648(v989, v990, v991, v992, v993, v994, v995, v996, v997, 0, v1000, v1016, 1, v1005, v1020, v1006, v1002, v1003, v1004, v1007, v1008, v1009, v1010, v1011, v1012, v1013, v1014, v1015, 3, 7, 2, 4, 8) :|: TRUE f_648(v989, v990, v991, v992, v993, v994, v995, v996, v997, 0, v1000, v1016, 1, v1005, v1020, v1006, v1002, v1003, v1004, v1007, v1008, v1009, v1010, v1011, v1012, v1013, v1014, v1015, 3, 7, 2, 4, 8) -> f_651(v989, v990, v991, v992, v993, v994, v995, v996, v997, 0, v1000, v1016, 1, v1005, v1020, v1006, v1003, v1002, v1004, v1007, v1008, v1009, v1010, v1011, v1012, v1013, v1014, v1015, 3, 7, 2, 4, 8) :|: 0 = 0 f_651(v989, v990, v991, v992, v993, v994, v995, v996, v997, 0, v1000, v1016, 1, v1005, v1020, v1006, v1003, v1002, v1004, v1007, v1008, v1009, v1010, v1011, v1012, v1013, v1014, v1015, 3, 7, 2, 4, 8) -> f_654(v989, v990, v991, v992, v993, v994, v995, v996, v997, 0, v1000, v1016, 1, v1005, v1020, v1006, v1003, v1002, v1004, v1007, v1008, v1009, v1010, v1011, v1012, v1013, v1014, v1015, 3, 7, 2, 4, 8) :|: 0 = 0 f_654(v989, v990, v991, v992, v993, v994, v995, v996, v997, 0, v1000, v1016, 1, v1005, v1020, v1006, v1003, v1002, v1004, v1007, v1008, v1009, v1010, v1011, v1012, v1013, v1014, v1015, 3, 7, 2, 4, 8) -> f_657(v989, v990, v991, v992, v993, v994, v995, v996, v997, 0, v1000, v1016, 1, v1005, v1020, v1006, v1002, v1004, v1007, v1008, v1009, v1010, v1011, v1012, v1013, v1014, v1015, v1003, 3, 7, 2, 4, 8) :|: 0 = 0 f_657(v989, v990, v991, v992, v993, v994, v995, v996, v997, 0, v1000, v1016, 1, v1005, v1020, v1006, v1002, v1004, v1007, v1008, v1009, v1010, v1011, v1012, v1013, v1014, v1015, v1003, 3, 7, 2, 4, 8) -> f_661(v989, v990, v991, v992, v993, v994, v995, v996, v997, 0, v1000, v1016, 1, v1005, v1020, v1006, v1002, v1004, v1007, v1008, v1009, v1010, v1011, v1012, v1013, v1014, v1015, v1003, 3, 7, 2, 4, 8) :|: v1020 != 0 && v1005 < v1009 && v1006 < v1010 && 3 <= v1009 && 3 <= v1010 f_661(v989, v990, v991, v992, v993, v994, v995, v996, v997, 0, v1000, v1016, 1, v1005, v1020, v1006, v1002, v1004, v1007, v1008, v1009, v1010, v1011, v1012, v1013, v1014, v1015, v1003, 3, 7, 2, 4, 8) -> f_664(v989, v990, v991, v992, v993, v994, v995, v996, v997, 0, v1000, v1016, 1, v1005, v1020, v1006, v1002, v1004, v1007, v1008, v1009, v1010, v1011, v1012, v1013, v1014, v1015, v1003, 3, 7, 2, 4, 8) :|: 0 = 0 f_664(v989, v990, v991, v992, v993, v994, v995, v996, v997, 0, v1000, v1016, 1, v1005, v1020, v1006, v1002, v1004, v1007, v1008, v1009, v1010, v1011, v1012, v1013, v1014, v1015, v1003, 3, 7, 2, 4, 8) -> f_667(v989, v990, v991, v992, v993, v994, v995, v996, v997, 0, v1000, v1016, 1, v1005, v1020, v1006, v1002, v1004, v1007, v1008, v1009, v1010, v1011, v1012, v1013, v1014, v1015, v1003, 3, 7, 2, 4, 8) :|: TRUE f_667(v989, v990, v991, v992, v993, v994, v995, v996, v997, 0, v1000, v1016, 1, v1005, v1020, v1006, v1002, v1004, v1007, v1008, v1009, v1010, v1011, v1012, v1013, v1014, v1015, v1003, 3, 7, 2, 4, 8) -> f_670(v989, v990, v991, v992, v993, v994, v995, v996, v997, 0, v1000, v1016, 1, v1005, v1020, v1006, v1004, v1007, v1008, v1009, v1010, v1011, v1012, v1013, v1014, v1015, v1002, v1003, 3, 7, 2, 4, 8) :|: 0 = 0 f_670(v989, v990, v991, v992, v993, v994, v995, v996, v997, 0, v1000, v1016, 1, v1005, v1020, v1006, v1004, v1007, v1008, v1009, v1010, v1011, v1012, v1013, v1014, v1015, v1002, v1003, 3, 7, 2, 4, 8) -> f_674(v989, v990, v991, v992, v993, v994, v995, v996, v997, 0, v1000, v1016, 1, v1005, v1020, v1006, v1242, v1004, v1007, v1008, v1009, v1010, v1011, v1012, v1013, v1014, v1015, v1002, v1003, 3, 7, 2, 4, 8) :|: v1242 = 1 + v1005 && 3 <= v1242 f_674(v989, v990, v991, v992, v993, v994, v995, v996, v997, 0, v1000, v1016, 1, v1005, v1020, v1006, v1242, v1004, v1007, v1008, v1009, v1010, v1011, v1012, v1013, v1014, v1015, v1002, v1003, 3, 7, 2, 4, 8) -> f_678(v989, v990, v991, v992, v993, v994, v995, v996, v997, 0, v1000, v1016, 1, v1005, v1020, v1006, v1242, v1004, v1007, v1008, v1009, v1010, v1011, v1012, v1013, v1014, v1015, v1002, v1003, 3, 7, 2, 4, 8) :|: TRUE f_678(v989, v990, v991, v992, v993, v994, v995, v996, v997, 0, v1000, v1016, 1, v1005, v1020, v1006, v1242, v1004, v1007, v1008, v1009, v1010, v1011, v1012, v1013, v1014, v1015, v1002, v1003, 3, 7, 2, 4, 8) -> f_682(v989, v990, v991, v992, v993, v994, v995, v996, v997, 0, v1000, v1016, 1, v1005, v1020, v1006, v1242, v1007, v1008, v1009, v1010, v1011, v1012, v1013, v1014, v1015, v1002, v1003, v1004, 3, 7, 2, 4, 8) :|: 0 = 0 f_682(v989, v990, v991, v992, v993, v994, v995, v996, v997, 0, v1000, v1016, 1, v1005, v1020, v1006, v1242, v1007, v1008, v1009, v1010, v1011, v1012, v1013, v1014, v1015, v1002, v1003, v1004, 3, 7, 2, 4, 8) -> f_685(v989, v990, v991, v992, v993, v994, v995, v996, v997, 0, v1000, v1016, 1, v1005, v1020, v1006, v1242, v1303, v1007, v1008, v1009, v1010, v1011, v1012, v1013, v1014, v1015, v1002, v1003, v1004, 3, 7, 2, 4, 8) :|: v1303 = 1 + v1006 && 3 <= v1303 f_685(v989, v990, v991, v992, v993, v994, v995, v996, v997, 0, v1000, v1016, 1, v1005, v1020, v1006, v1242, v1303, v1007, v1008, v1009, v1010, v1011, v1012, v1013, v1014, v1015, v1002, v1003, v1004, 3, 7, 2, 4, 8) -> f_688(v989, v990, v991, v992, v993, v994, v995, v996, v997, 0, v1000, v1016, 1, v1005, v1020, v1006, v1242, v1303, v1007, v1008, v1009, v1010, v1011, v1012, v1013, v1014, v1015, v1002, v1003, v1004, 3, 7, 2, 4, 8) :|: TRUE f_688(v989, v990, v991, v992, v993, v994, v995, v996, v997, 0, v1000, v1016, 1, v1005, v1020, v1006, v1242, v1303, v1007, v1008, v1009, v1010, v1011, v1012, v1013, v1014, v1015, v1002, v1003, v1004, 3, 7, 2, 4, 8) -> f_691(v989, v990, v991, v992, v993, v994, v995, v996, v997, 0, v1000, v1016, 1, v1005, v1020, v1006, v1242, v1303, v1007, v1008, v1009, v1010, v1011, v1012, v1013, v1014, v1015, v1002, v1003, v1004, 3, 7, 2, 4, 8) :|: TRUE f_691(v989, v990, v991, v992, v993, v994, v995, v996, v997, 0, v1000, v1016, 1, v1005, v1020, v1006, v1242, v1303, v1007, v1008, v1009, v1010, v1011, v1012, v1013, v1014, v1015, v1002, v1003, v1004, 3, 7, 2, 4, 8) -> f_619(v989, v990, v991, v992, v993, v994, v995, v996, v997, 0, v1000, v1016, 1, v1005, v1020, v1006, v1242, v1303, v1007, v1008, v1009, v1010, v1011, v1012, v1013, v1014, v1015, 3, 7, 2, 4, 8) :|: TRUE f_619(v989, v990, v991, v992, v993, v994, v995, v996, v997, 0, v999, v1000, 1, v1002, v1003, v1004, v1005, v1006, v1007, v1008, v1009, v1010, v1011, v1012, v1013, v1014, v1015, 3, 7, 2, 4, 8) -> f_620(v989, v990, v991, v992, v993, v994, v995, v996, v997, 0, v1000, 1, v1002, v1003, v1004, v1005, v1006, v1007, v1008, v1009, v1010, v1011, v1012, v1013, v1014, v1015, 3, 7, 2, 4, 8) :|: 0 = 0 Combined rules. Obtained 2 rulesP rules: f_620(v989:0, v990:0, v991:0, v992:0, v993:0, v994:0, v995:0, v996:0, v997:0, 0, 1 + v1016:0, 1, v1002:0, v1003:0, v1004:0, v1005:0, v1006:0, v1007:0, v1008:0, v1009:0, v1010:0, v1011:0, v1012:0, v1013:0, v1014:0, v1015:0, 3, 7, 2, 4, 8) -> f_620(v989:0, v990:0, v991:0, v992:0, v993:0, v994:0, v995:0, v996:0, v997:0, 0, v1016:0, 1, v1005:0, v1018:0, v1006:0, 1 + v1005:0, 1 + v1006:0, v1007:0, v1008:0, v1009:0, v1010:0, v1011:0, v1012:0, v1013:0, v1014:0, v1015:0, 3, 7, 2, 4, 8) :|: v1016:0 > 0 && v991:0 > 2 && v1009:0 > v1005:0 && v1018:0 < 0 && v1010:0 > v1006:0 && v1009:0 > 2 && v1010:0 > 2 && v1006:0 > 1 && v1005:0 > 1 f_620(v989:0, v990:0, v991:0, v992:0, v993:0, v994:0, v995:0, v996:0, v997:0, 0, 1 + v1016:0, 1, v1002:0, v1003:0, v1004:0, v1005:0, v1006:0, v1007:0, v1008:0, v1009:0, v1010:0, v1011:0, v1012:0, v1013:0, v1014:0, v1015:0, 3, 7, 2, 4, 8) -> f_620(v989:0, v990:0, v991:0, v992:0, v993:0, v994:0, v995:0, v996:0, v997:0, 0, v1016:0, 1, v1005:0, v1018:0, v1006:0, 1 + v1005:0, 1 + v1006:0, v1007:0, v1008:0, v1009:0, v1010:0, v1011:0, v1012:0, v1013:0, v1014:0, v1015:0, 3, 7, 2, 4, 8) :|: v1016:0 > 0 && v991:0 > 2 && v1009:0 > v1005:0 && v1018:0 > 0 && v1010:0 > v1006:0 && v1009:0 > 2 && v1010:0 > 2 && v1006:0 > 1 && v1005:0 > 1 Filtered unneeded arguments: f_620(x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15, x16, x17, x18, x19, x20, x21, x22, x23, x24, x25, x26, x27, x28, x29, x30, x31) -> f_620(x3, x11, x16, x17, x20, x21) Removed division, modulo operations, cleaned up constraints. Obtained 1 rules.P rules: f_620(v991:0, sum~cons_1~v1016:0, v1005:0, v1006:0, v1009:0, v1010:0) -> f_620(v991:0, v1016:0, 1 + v1005:0, 1 + v1006:0, v1009:0, v1010:0) :|: v991:0 > 2 && v1016:0 > 0 && v1009:0 > v1005:0 && v1010:0 > v1006:0 && v1009:0 > 2 && v1010:0 > 2 && v1005:0 > 1 && v1006:0 > 1 && sum~cons_1~v1016:0 = 1 + v1016:0 ---------------------------------------- (8) Obligation: Rules: f_620(v991:0, sum~cons_1~v1016:0, v1005:0, v1006:0, v1009:0, v1010:0) -> f_620(v991:0, v1016:0, 1 + v1005:0, 1 + v1006:0, v1009:0, v1010:0) :|: v991:0 > 2 && v1016:0 > 0 && v1009:0 > v1005:0 && v1010:0 > v1006:0 && v1009:0 > 2 && v1010:0 > 2 && v1005:0 > 1 && v1006:0 > 1 && sum~cons_1~v1016:0 = 1 + v1016:0 ---------------------------------------- (9) IntTRSCompressionProof (EQUIVALENT) Compressed rules. ---------------------------------------- (10) Obligation: Rules: f_620(v991:0:0, sum~cons_1~v1016:0:0, v1005:0:0, v1006:0:0, v1009:0:0, v1010:0:0) -> f_620(v991:0:0, v1016:0:0, 1 + v1005:0:0, 1 + v1006:0:0, v1009:0:0, v1010:0:0) :|: v1005:0:0 > 1 && v1006:0:0 > 1 && v1010:0:0 > 2 && v1009:0:0 > 2 && v1010:0:0 > v1006:0:0 && v1009:0:0 > v1005:0:0 && v1016:0:0 > 0 && v991:0:0 > 2 && sum~cons_1~v1016:0:0 = 1 + v1016:0:0 ---------------------------------------- (11) PolynomialOrderProcessor (EQUIVALENT) Found the following polynomial interpretation: [f_620(x, x1, x2, x3, x4, x5)] = -2 + x1 The following rules are decreasing: f_620(v991:0:0, sum~cons_1~v1016:0:0, v1005:0:0, v1006:0:0, v1009:0:0, v1010:0:0) -> f_620(v991:0:0, v1016:0:0, 1 + v1005:0:0, 1 + v1006:0:0, v1009:0:0, v1010:0:0) :|: v1005:0:0 > 1 && v1006:0:0 > 1 && v1010:0:0 > 2 && v1009:0:0 > 2 && v1010:0:0 > v1006:0:0 && v1009:0:0 > v1005:0:0 && v1016:0:0 > 0 && v991:0:0 > 2 && sum~cons_1~v1016:0:0 = 1 + v1016:0:0 The following rules are bounded: f_620(v991:0:0, sum~cons_1~v1016:0:0, v1005:0:0, v1006:0:0, v1009:0:0, v1010:0:0) -> f_620(v991:0:0, v1016:0:0, 1 + v1005:0:0, 1 + v1006:0:0, v1009:0:0, v1010:0:0) :|: v1005:0:0 > 1 && v1006:0:0 > 1 && v1010:0:0 > 2 && v1009:0:0 > 2 && v1010:0:0 > v1006:0:0 && v1009:0:0 > v1005:0:0 && v1016:0:0 > 0 && v991:0:0 > 2 && sum~cons_1~v1016:0:0 = 1 + v1016:0:0 ---------------------------------------- (12) YES