/export/starexec/sandbox/solver/bin/starexec_run_c /export/starexec/sandbox/benchmark/theBenchmark.c /export/starexec/sandbox/output/output_files -------------------------------------------------------------------------------- YES proof of /export/starexec/sandbox/benchmark/theBenchmark.c # AProVE Commit ID: 48fb2092695e11cc9f56e44b17a92a5f88ffb256 marcel 20180622 unpublished dirty Termination of the given C Problem could be proven: (0) C Problem (1) CToLLVMProof [EQUIVALENT, 179 ms] (2) LLVM problem (3) LLVMToTerminationGraphProof [EQUIVALENT, 4305 ms] (4) LLVM Symbolic Execution Graph (5) SymbolicExecutionGraphToSCCProof [SOUND, 0 ms] (6) LLVM Symbolic Execution SCC (7) SCC2IRS [SOUND, 93 ms] (8) IntTRS (9) PolynomialOrderProcessor [EQUIVALENT, 12 ms] (10) YES ---------------------------------------- (0) Obligation: c file /export/starexec/sandbox/benchmark/theBenchmark.c ---------------------------------------- (1) CToLLVMProof (EQUIVALENT) Compiled c-file /export/starexec/sandbox/benchmark/theBenchmark.c to LLVM. ---------------------------------------- (2) Obligation: LLVM Problem Aliases: Data layout: "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" Machine: "x86_64-pc-linux-gnu" Type definitions: Global variables: Function declarations and definitions: *BasicFunctionTypename: "__VERIFIER_nondet_int" returnParam: i32 parameters: () variableLength: false visibilityType: DEFAULT callingConvention: ccc *BasicFunctionTypename: "test_fun" linkageType: EXTERNALLY_VISIBLE returnParam: i32 parameters: (x i32, y i32) variableLength: false visibilityType: DEFAULT callingConvention: ccc 0: %1 = alloca i32, align 4 %2 = alloca i32, align 4 %x_ref = alloca *i32, align 8 %y_ref = alloca *i32, align 8 %c = alloca *i32, align 8 store %x, %1 store %y, %2 %3 = alloca i8, numElementsLit: 4 %4 = bitcast *i8 %3 to *i32 store %4, %x_ref %5 = alloca i8, numElementsLit: 4 %6 = bitcast *i8 %5 to *i32 store %6, %y_ref %7 = alloca i8, numElementsLit: 4 %8 = bitcast *i8 %7 to *i32 store %8, %c %9 = load %1 %10 = load %x_ref store %9, %10 %11 = load %2 %12 = load %y_ref store %11, %12 %13 = load %c store 0, %13 br %14 14: %15 = load %x_ref %16 = load %15 %17 = load %y_ref %18 = load %17 %19 = icmp sgt %16 %18 br %19, %20, %29 20: %21 = load %y_ref %22 = load %21 %23 = add %22 1 %24 = load %y_ref store %23, %24 %25 = load %c %26 = load %25 %27 = add %26 1 %28 = load %c store %27, %28 br %14 29: %30 = load %c %31 = load %30 ret %31 *BasicFunctionTypename: "main" linkageType: EXTERNALLY_VISIBLE returnParam: i32 parameters: () variableLength: false visibilityType: DEFAULT callingConvention: ccc 0: %1 = alloca i32, align 4 store 0, %1 %2 = call i32 @__VERIFIER_nondet_int() %3 = call i32 @__VERIFIER_nondet_int() %4 = call i32 @test_fun(i32 %2, i32 %3) ret %4 Analyze Termination of all function calls matching the pattern: main() ---------------------------------------- (3) LLVMToTerminationGraphProof (EQUIVALENT) Constructed symbolic execution graph for LLVM program and proved memory safety. ---------------------------------------- (4) Obligation: SE Graph ---------------------------------------- (5) SymbolicExecutionGraphToSCCProof (SOUND) Splitted symbolic execution graph to 1 SCC. ---------------------------------------- (6) Obligation: SCC ---------------------------------------- (7) SCC2IRS (SOUND) Transformed LLVM symbolic execution graph SCC into a rewrite problem. Log: Generated rules. Obtained 19 rulesP rules: f_362(v182, v183, v184, v185, v186, v187, v188, v189, v190, v191, v192, 1, v194, v195, v196, v197, v198, v199, v200, v201, v202, v203, v204, v205, v206, 0, 3, 7, 4, 8) -> f_363(v182, v183, v184, v185, v186, v187, v188, v189, v190, v191, v192, 1, v194, v195, v196, v197, v198, v199, v200, v201, v202, v203, v204, v205, v206, 0, 3, 7, 4, 8) :|: 0 = 0 f_363(v182, v183, v184, v185, v186, v187, v188, v189, v190, v191, v192, 1, v194, v195, v196, v197, v198, v199, v200, v201, v202, v203, v204, v205, v206, 0, 3, 7, 4, 8) -> f_364(v182, v183, v184, v185, v186, v187, v188, v189, v190, v191, v192, 1, v194, v195, v196, v197, v198, v199, v200, v201, v202, v203, v204, v205, v206, 0, 3, 7, 4, 8) :|: 0 = 0 f_364(v182, v183, v184, v185, v186, v187, v188, v189, v190, v191, v192, 1, v194, v195, v196, v197, v198, v199, v200, v201, v202, v203, v204, v205, v206, 0, 3, 7, 4, 8) -> f_365(v182, v183, v184, v185, v186, v187, v188, v189, v190, v191, v194, 1, v192, v195, v196, v197, v198, v199, v200, v201, v202, v203, v204, v205, v206, 0, 3, 7, 4, 8) :|: 0 = 0 f_365(v182, v183, v184, v185, v186, v187, v188, v189, v190, v191, v194, 1, v192, v195, v196, v197, v198, v199, v200, v201, v202, v203, v204, v205, v206, 0, 3, 7, 4, 8) -> f_366(v182, v183, v184, v185, v186, v187, v188, v189, v190, v191, v194, 1, v192, v195, v196, v197, v198, v199, v200, v201, v202, v203, v204, v205, v206, 0, 3, 7, 4, 8) :|: v194 < v182 f_366(v182, v183, v184, v185, v186, v187, v188, v189, v190, v191, v194, 1, v192, v195, v196, v197, v198, v199, v200, v201, v202, v203, v204, v205, v206, 0, 3, 7, 4, 8) -> f_368(v182, v183, v184, v185, v186, v187, v188, v189, v190, v191, v194, 1, v192, v195, v196, v197, v198, v199, v200, v201, v202, v203, v204, v205, v206, 0, 3, 7, 4, 8) :|: 0 = 0 f_368(v182, v183, v184, v185, v186, v187, v188, v189, v190, v191, v194, 1, v192, v195, v196, v197, v198, v199, v200, v201, v202, v203, v204, v205, v206, 0, 3, 7, 4, 8) -> f_370(v182, v183, v184, v185, v186, v187, v188, v189, v190, v191, v194, 1, v192, v195, v196, v197, v198, v199, v200, v201, v202, v203, v204, v205, v206, 0, 3, 7, 4, 8) :|: TRUE f_370(v182, v183, v184, v185, v186, v187, v188, v189, v190, v191, v194, 1, v192, v195, v196, v197, v198, v199, v200, v201, v202, v203, v204, v205, v206, 0, 3, 7, 4, 8) -> f_372(v182, v183, v184, v185, v186, v187, v188, v189, v190, v191, v194, 1, v192, v195, v196, v197, v198, v199, v200, v201, v202, v203, v204, v205, v206, 0, 3, 7, 4, 8) :|: 0 = 0 f_372(v182, v183, v184, v185, v186, v187, v188, v189, v190, v191, v194, 1, v192, v195, v196, v197, v198, v199, v200, v201, v202, v203, v204, v205, v206, 0, 3, 7, 4, 8) -> f_374(v182, v183, v184, v185, v186, v187, v188, v189, v190, v191, v194, 1, v195, v196, v197, v198, v199, v200, v201, v202, v203, v204, v205, v206, 0, 3, 7, 4, 8) :|: 0 = 0 f_374(v182, v183, v184, v185, v186, v187, v188, v189, v190, v191, v194, 1, v195, v196, v197, v198, v199, v200, v201, v202, v203, v204, v205, v206, 0, 3, 7, 4, 8) -> f_376(v182, v183, v184, v185, v186, v187, v188, v189, v190, v191, v194, 1, v208, v195, v196, v197, v198, v199, v200, v201, v202, v203, v204, v205, v206, 0, 3, 7, 4, 8) :|: v208 = 1 + v194 f_376(v182, v183, v184, v185, v186, v187, v188, v189, v190, v191, v194, 1, v208, v195, v196, v197, v198, v199, v200, v201, v202, v203, v204, v205, v206, 0, 3, 7, 4, 8) -> f_378(v182, v183, v184, v185, v186, v187, v188, v189, v190, v191, v194, 1, v208, v195, v196, v197, v198, v199, v200, v201, v202, v203, v204, v205, v206, 0, 3, 7, 4, 8) :|: 0 = 0 f_378(v182, v183, v184, v185, v186, v187, v188, v189, v190, v191, v194, 1, v208, v195, v196, v197, v198, v199, v200, v201, v202, v203, v204, v205, v206, 0, 3, 7, 4, 8) -> f_379(v182, v183, v184, v185, v186, v187, v188, v189, v190, v191, v194, 1, v208, v195, v196, v197, v198, v199, v200, v201, v202, v203, v204, v205, v206, 0, 3, 7, 4, 8) :|: TRUE f_379(v182, v183, v184, v185, v186, v187, v188, v189, v190, v191, v194, 1, v208, v195, v196, v197, v198, v199, v200, v201, v202, v203, v204, v205, v206, 0, 3, 7, 4, 8) -> f_380(v182, v183, v184, v185, v186, v187, v188, v189, v190, v191, v194, 1, v208, v195, v196, v197, v198, v199, v200, v201, v202, v203, v204, v205, v206, 0, 3, 7, 4, 8) :|: 0 = 0 f_380(v182, v183, v184, v185, v186, v187, v188, v189, v190, v191, v194, 1, v208, v195, v196, v197, v198, v199, v200, v201, v202, v203, v204, v205, v206, 0, 3, 7, 4, 8) -> f_381(v182, v183, v184, v185, v186, v187, v188, v189, v190, v191, v194, 1, v208, v196, v197, v198, v199, v200, v201, v202, v203, v204, v205, v206, 0, 3, 7, 4, 8) :|: 0 = 0 f_381(v182, v183, v184, v185, v186, v187, v188, v189, v190, v191, v194, 1, v208, v196, v197, v198, v199, v200, v201, v202, v203, v204, v205, v206, 0, 3, 7, 4, 8) -> f_382(v182, v183, v184, v185, v186, v187, v188, v189, v190, v191, v194, 1, v208, v196, v210, v197, v198, v199, v200, v201, v202, v203, v204, v205, v206, 0, 3, 7, 4, 8, 2) :|: v210 = 1 + v196 && 2 <= v210 f_382(v182, v183, v184, v185, v186, v187, v188, v189, v190, v191, v194, 1, v208, v196, v210, v197, v198, v199, v200, v201, v202, v203, v204, v205, v206, 0, 3, 7, 4, 8, 2) -> f_383(v182, v183, v184, v185, v186, v187, v188, v189, v190, v191, v194, 1, v208, v196, v210, v197, v198, v199, v200, v201, v202, v203, v204, v205, v206, 0, 3, 7, 4, 8, 2) :|: 0 = 0 f_383(v182, v183, v184, v185, v186, v187, v188, v189, v190, v191, v194, 1, v208, v196, v210, v197, v198, v199, v200, v201, v202, v203, v204, v205, v206, 0, 3, 7, 4, 8, 2) -> f_384(v182, v183, v184, v185, v186, v187, v188, v189, v190, v191, v194, 1, v208, v196, v210, v197, v198, v199, v200, v201, v202, v203, v204, v205, v206, 0, 3, 7, 4, 8, 2) :|: TRUE f_384(v182, v183, v184, v185, v186, v187, v188, v189, v190, v191, v194, 1, v208, v196, v210, v197, v198, v199, v200, v201, v202, v203, v204, v205, v206, 0, 3, 7, 4, 8, 2) -> f_385(v182, v183, v184, v185, v186, v187, v188, v189, v190, v191, v194, 1, v208, v196, v210, v197, v198, v199, v200, v201, v202, v203, v204, v205, v206, 0, 3, 7, 4, 8, 2) :|: TRUE f_385(v182, v183, v184, v185, v186, v187, v188, v189, v190, v191, v194, 1, v208, v196, v210, v197, v198, v199, v200, v201, v202, v203, v204, v205, v206, 0, 3, 7, 4, 8, 2) -> f_361(v182, v183, v184, v185, v186, v187, v188, v189, v190, v191, v194, 1, v208, v196, v210, v197, v198, v199, v200, v201, v202, v203, v204, v205, v206, 0, 3, 7, 4, 8) :|: TRUE f_361(v182, v183, v184, v185, v186, v187, v188, v189, v190, v191, v192, 1, v194, v195, v196, v197, v198, v199, v200, v201, v202, v203, v204, v205, v206, 0, 3, 7, 4, 8) -> f_362(v182, v183, v184, v185, v186, v187, v188, v189, v190, v191, v192, 1, v194, v195, v196, v197, v198, v199, v200, v201, v202, v203, v204, v205, v206, 0, 3, 7, 4, 8) :|: 0 = 0 Combined rules. Obtained 1 rulesP rules: f_362(v182:0, v183:0, v184:0, v185:0, v186:0, v187:0, v188:0, v189:0, v190:0, v191:0, v192:0, 1, v194:0, v195:0, v196:0, v197:0, v198:0, v199:0, v200:0, v201:0, v202:0, v203:0, v204:0, v205:0, v206:0, 0, 3, 7, 4, 8) -> f_362(v182:0, v183:0, v184:0, v185:0, v186:0, v187:0, v188:0, v189:0, v190:0, v191:0, v194:0, 1, 1 + v194:0, v196:0, 1 + v196:0, v197:0, v198:0, v199:0, v200:0, v201:0, v202:0, v203:0, v204:0, v205:0, v206:0, 0, 3, 7, 4, 8) :|: v196:0 > 0 && v194:0 < v182:0 Filtered unneeded arguments: f_362(x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15, x16, x17, x18, x19, x20, x21, x22, x23, x24, x25, x26, x27, x28, x29, x30) -> f_362(x1, x13, x15) Removed division, modulo operations, cleaned up constraints. Obtained 1 rules.P rules: f_362(v182:0, v194:0, v196:0) -> f_362(v182:0, 1 + v194:0, 1 + v196:0) :|: v196:0 > 0 && v194:0 < v182:0 ---------------------------------------- (8) Obligation: Rules: f_362(v182:0, v194:0, v196:0) -> f_362(v182:0, 1 + v194:0, 1 + v196:0) :|: v196:0 > 0 && v194:0 < v182:0 ---------------------------------------- (9) PolynomialOrderProcessor (EQUIVALENT) Found the following polynomial interpretation: [f_362(x, x1, x2)] = x - x1 The following rules are decreasing: f_362(v182:0, v194:0, v196:0) -> f_362(v182:0, 1 + v194:0, 1 + v196:0) :|: v196:0 > 0 && v194:0 < v182:0 The following rules are bounded: f_362(v182:0, v194:0, v196:0) -> f_362(v182:0, 1 + v194:0, 1 + v196:0) :|: v196:0 > 0 && v194:0 < v182:0 ---------------------------------------- (10) YES