/export/starexec/sandbox2/solver/bin/starexec_run_c /export/starexec/sandbox2/benchmark/theBenchmark.c /export/starexec/sandbox2/output/output_files


--------------------------------------------------------------------------------


YES
proof of /export/starexec/sandbox2/benchmark/theBenchmark.c
# AProVE Commit ID: 48fb2092695e11cc9f56e44b17a92a5f88ffb256 marcel 20180622 unpublished dirty


Termination of the given C Problem could be proven:

(0) C Problem
(1) CToLLVMProof [EQUIVALENT, 176 ms]
(2) LLVM problem
(3) LLVMToTerminationGraphProof [EQUIVALENT, 1800 ms]
(4) LLVM Symbolic Execution Graph
(5) SymbolicExecutionGraphToSCCProof [SOUND, 0 ms]
(6) LLVM Symbolic Execution SCC
(7) SCC2IRS [SOUND, 0 ms]
(8) IntTRS
(9) IntTRSCompressionProof [EQUIVALENT, 0 ms]
(10) IntTRS
(11) RankingReductionPairProof [EQUIVALENT, 33 ms]
(12) YES


----------------------------------------

(0)
Obligation:
c file /export/starexec/sandbox2/benchmark/theBenchmark.c
----------------------------------------

(1) CToLLVMProof (EQUIVALENT)
Compiled c-file /export/starexec/sandbox2/benchmark/theBenchmark.c to LLVM.
----------------------------------------

(2)
Obligation:
LLVM Problem

Aliases:

Data layout:

"e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"

Machine:

"x86_64-pc-linux-gnu"

Type definitions:

Global variables:

Function declarations and definitions:

*BasicFunctionTypename: "__VERIFIER_nondet_int" returnParam: i32 parameters: () variableLength: false visibilityType: DEFAULT callingConvention: ccc
*BasicFunctionTypename: "test_fun" linkageType: EXTERNALLY_VISIBLE returnParam: i32 parameters: (x i32, y i32) variableLength: false visibilityType: DEFAULT callingConvention: ccc
	0:
		%1 = alloca i32, align 4
		%2 = alloca i32, align 4
		%3 = alloca i32, align 4
		%x_ref = alloca *i32, align 8
		%y_ref = alloca *i32, align 8
		store %x, %2
		store %y, %3
		%4 = alloca i8, numElementsLit: 4
		%5 = bitcast *i8 %4 to *i32
		store %5, %x_ref
		%6 = alloca i8, numElementsLit: 4
		%7 = bitcast *i8 %6 to *i32
		store %7, %y_ref
		%8 = load %2
		%9 = load %x_ref
		store %8, %9
		%10 = load %3
		%11 = load %y_ref
		store %10, %11
		%12 = load %x_ref
		%13 = load %12
		%14 = icmp sle %13 0
		br %14, %15, %18
	15:
		%16 = load %y_ref
		%17 = load %16
		store %17, %1
		br %42
	18:
		br %19
	19:
		%20 = load %x_ref
		%21 = load %20
		%22 = load %y_ref
		%23 = load %22
		%24 = icmp sgt %21 %23
		br %24, %25, %39
	25:
		%26 = load %x_ref
		%27 = load %26
		%28 = icmp sle %27 0
		br %28, %29, %32
	29:
		%30 = load %y_ref
		%31 = load %30
		store %31, %1
		br %42
	32:
		%33 = load %y_ref
		%34 = load %33
		%35 = load %x_ref
		%36 = load %35
		%37 = add %34 %36
		%38 = load %y_ref
		store %37, %38
		br %19
	39:
		%40 = load %y_ref
		%41 = load %40
		store %41, %1
		br %42
	42:
		%43 = load %1
		ret %43

*BasicFunctionTypename: "main" linkageType: EXTERNALLY_VISIBLE returnParam: i32 parameters: () variableLength: false visibilityType: DEFAULT callingConvention: ccc
	0:
		%1 = alloca i32, align 4
		store 0, %1
		%2 = call i32 @__VERIFIER_nondet_int()
		%3 = call i32 @__VERIFIER_nondet_int()
		%4 = call i32 @test_fun(i32 %2, i32 %3)
		ret %4


Analyze Termination of all function calls matching the pattern:
main()
----------------------------------------

(3) LLVMToTerminationGraphProof (EQUIVALENT)
Constructed symbolic execution graph for LLVM program and proved memory safety.
----------------------------------------

(4)
Obligation:
SE Graph
----------------------------------------

(5) SymbolicExecutionGraphToSCCProof (SOUND)
Splitted symbolic execution graph to 1 SCC.
----------------------------------------

(6)
Obligation:
SCC
----------------------------------------

(7) SCC2IRS (SOUND)
Transformed LLVM symbolic execution graph SCC into a rewrite problem. Log: 
Generated rules. Obtained 20 rulesP rules:
f_316(v59, v60, v61, v62, v63, v64, v65, v66, v67, 0, v69, 1, v71, v72, v73, v74, v75, v76, v77, v78, v79, v80, 3, 7, 4, 8) -> f_317(v59, v60, v61, v62, v63, v64, v65, v66, v67, 0, v69, 1, v71, v72, v73, v74, v75, v76, v77, v78, v79, v80, 3, 7, 4, 8) :|: 0 = 0
f_317(v59, v60, v61, v62, v63, v64, v65, v66, v67, 0, v69, 1, v71, v72, v73, v74, v75, v76, v77, v78, v79, v80, 3, 7, 4, 8) -> f_318(v59, v60, v61, v62, v63, v64, v65, v66, v67, 0, v69, 1, v71, v72, v73, v74, v75, v76, v77, v78, v79, v80, 3, 7, 4, 8) :|: 0 = 0
f_318(v59, v60, v61, v62, v63, v64, v65, v66, v67, 0, v69, 1, v71, v72, v73, v74, v75, v76, v77, v78, v79, v80, 3, 7, 4, 8) -> f_319(v59, v60, v61, v62, v63, v64, v65, v66, v67, 0, v71, 1, v69, v72, v73, v74, v75, v76, v77, v78, v79, v80, 3, 7, 4, 8) :|: 0 = 0
f_319(v59, v60, v61, v62, v63, v64, v65, v66, v67, 0, v71, 1, v69, v72, v73, v74, v75, v76, v77, v78, v79, v80, 3, 7, 4, 8) -> f_320(v59, v60, v61, v62, v63, v64, v65, v66, v67, 0, v71, 1, v69, v72, v73, v74, v75, v76, v77, v78, v79, v80, 3, 7, 4, 8) :|: v71 < v59 && 1 + v69 <= 0
f_320(v59, v60, v61, v62, v63, v64, v65, v66, v67, 0, v71, 1, v69, v72, v73, v74, v75, v76, v77, v78, v79, v80, 3, 7, 4, 8) -> f_322(v59, v60, v61, v62, v63, v64, v65, v66, v67, 0, v71, 1, v69, v72, v73, v74, v75, v76, v77, v78, v79, v80, 3, 7, 4, 8) :|: 0 = 0
f_322(v59, v60, v61, v62, v63, v64, v65, v66, v67, 0, v71, 1, v69, v72, v73, v74, v75, v76, v77, v78, v79, v80, 3, 7, 4, 8) -> f_324(v59, v60, v61, v62, v63, v64, v65, v66, v67, 0, v71, 1, v69, v72, v73, v74, v75, v76, v77, v78, v79, v80, 3, 7, 4, 8) :|: TRUE
f_324(v59, v60, v61, v62, v63, v64, v65, v66, v67, 0, v71, 1, v69, v72, v73, v74, v75, v76, v77, v78, v79, v80, 3, 7, 4, 8) -> f_326(v59, v60, v61, v62, v63, v64, v65, v66, v67, 0, v71, 1, v69, v72, v73, v74, v75, v76, v77, v78, v79, v80, 3, 7, 4, 8) :|: 0 = 0
f_326(v59, v60, v61, v62, v63, v64, v65, v66, v67, 0, v71, 1, v69, v72, v73, v74, v75, v76, v77, v78, v79, v80, 3, 7, 4, 8) -> f_328(v59, v60, v61, v62, v63, v64, v65, v66, v67, 0, v71, 1, v69, v72, v73, v74, v75, v76, v77, v78, v79, v80, 3, 7, 4, 8) :|: 0 = 0
f_328(v59, v60, v61, v62, v63, v64, v65, v66, v67, 0, v71, 1, v69, v72, v73, v74, v75, v76, v77, v78, v79, v80, 3, 7, 4, 8) -> f_330(v59, v60, v61, v62, v63, v64, v65, v66, v67, 0, v71, 1, v69, v72, v73, v74, v75, v76, v77, v78, v79, v80, 3, 7, 4, 8) :|: 0 = 0
f_330(v59, v60, v61, v62, v63, v64, v65, v66, v67, 0, v71, 1, v69, v72, v73, v74, v75, v76, v77, v78, v79, v80, 3, 7, 4, 8) -> f_332(v59, v60, v61, v62, v63, v64, v65, v66, v67, 0, v71, 1, v69, v72, v73, v74, v75, v76, v77, v78, v79, v80, 3, 7, 4, 8) :|: TRUE
f_332(v59, v60, v61, v62, v63, v64, v65, v66, v67, 0, v71, 1, v69, v72, v73, v74, v75, v76, v77, v78, v79, v80, 3, 7, 4, 8) -> f_334(v59, v60, v61, v62, v63, v64, v65, v66, v67, 0, v71, 1, v69, v72, v73, v74, v75, v76, v77, v78, v79, v80, 3, 7, 4, 8) :|: 0 = 0
f_334(v59, v60, v61, v62, v63, v64, v65, v66, v67, 0, v71, 1, v69, v72, v73, v74, v75, v76, v77, v78, v79, v80, 3, 7, 4, 8) -> f_336(v59, v60, v61, v62, v63, v64, v65, v66, v67, 0, v71, 1, v72, v73, v74, v75, v76, v77, v78, v79, v80, 3, 7, 4, 8) :|: 0 = 0
f_336(v59, v60, v61, v62, v63, v64, v65, v66, v67, 0, v71, 1, v72, v73, v74, v75, v76, v77, v78, v79, v80, 3, 7, 4, 8) -> f_338(v59, v60, v61, v62, v63, v64, v65, v66, v67, 0, v71, 1, v72, v73, v74, v75, v76, v77, v78, v79, v80, 3, 7, 4, 8) :|: 0 = 0
f_338(v59, v60, v61, v62, v63, v64, v65, v66, v67, 0, v71, 1, v72, v73, v74, v75, v76, v77, v78, v79, v80, 3, 7, 4, 8) -> f_339(v59, v60, v61, v62, v63, v64, v65, v66, v67, 0, v71, 1, v72, v73, v74, v75, v76, v77, v78, v79, v80, 3, 7, 4, 8) :|: 0 = 0
f_339(v59, v60, v61, v62, v63, v64, v65, v66, v67, 0, v71, 1, v72, v73, v74, v75, v76, v77, v78, v79, v80, 3, 7, 4, 8) -> f_340(v59, v60, v61, v62, v63, v64, v65, v66, v67, 0, v71, 1, v83, v72, v73, v74, v75, v76, v77, v78, v79, v80, 3, 7, 4, 8) :|: v83 = v71 + v59
f_340(v59, v60, v61, v62, v63, v64, v65, v66, v67, 0, v71, 1, v83, v72, v73, v74, v75, v76, v77, v78, v79, v80, 3, 7, 4, 8) -> f_341(v59, v60, v61, v62, v63, v64, v65, v66, v67, 0, v71, 1, v83, v72, v73, v74, v75, v76, v77, v78, v79, v80, 3, 7, 4, 8) :|: 0 = 0
f_341(v59, v60, v61, v62, v63, v64, v65, v66, v67, 0, v71, 1, v83, v72, v73, v74, v75, v76, v77, v78, v79, v80, 3, 7, 4, 8) -> f_342(v59, v60, v61, v62, v63, v64, v65, v66, v67, 0, v71, 1, v83, v72, v73, v74, v75, v76, v77, v78, v79, v80, 3, 7, 4, 8) :|: TRUE
f_342(v59, v60, v61, v62, v63, v64, v65, v66, v67, 0, v71, 1, v83, v72, v73, v74, v75, v76, v77, v78, v79, v80, 3, 7, 4, 8) -> f_343(v59, v60, v61, v62, v63, v64, v65, v66, v67, 0, v71, 1, v83, v72, v73, v74, v75, v76, v77, v78, v79, v80, 3, 7, 4, 8) :|: TRUE
f_343(v59, v60, v61, v62, v63, v64, v65, v66, v67, 0, v71, 1, v83, v72, v73, v74, v75, v76, v77, v78, v79, v80, 3, 7, 4, 8) -> f_315(v59, v60, v61, v62, v63, v64, v65, v66, v67, 0, v71, 1, v83, v72, v73, v74, v75, v76, v77, v78, v79, v80, 3, 7, 4, 8) :|: v60 < v59 && 1 <= v59 && 1 <= v61 && 1 <= v62 && 1 <= v63 && 1 <= v64 && 1 <= v65 && 1 <= v66 && 1 <= v67 && 1 <= v72 && 4 <= v73 && 4 <= v74 && 4 <= v75 && 4 <= v76 && 8 <= v77 && 8 <= v78 && 4 <= v79 && 4 <= v80 && v72 <= v73 && v61 <= v74 && v62 <= v75 && v63 <= v76 && v64 <= v77 && v65 <= v78 && v66 <= v79 && v67 <= v80
f_315(v59, v60, v61, v62, v63, v64, v65, v66, v67, 0, v69, 1, v71, v72, v73, v74, v75, v76, v77, v78, v79, v80, 3, 7, 4, 8) -> f_316(v59, v60, v61, v62, v63, v64, v65, v66, v67, 0, v69, 1, v71, v72, v73, v74, v75, v76, v77, v78, v79, v80, 3, 7, 4, 8) :|: 0 = 0
Combined rules. Obtained 1 rulesP rules:
f_316(v59:0, v60:0, v61:0, v62:0, v63:0, v64:0, v65:0, v66:0, v67:0, 0, v69:0, 1, v71:0, v72:0, v73:0, v74:0, v75:0, v76:0, v77:0, v78:0, v79:0, v80:0, 3, 7, 4, 8) -> f_316(v59:0, v60:0, v61:0, v62:0, v63:0, v64:0, v65:0, v66:0, v67:0, 0, v71:0, 1, v71:0 + v59:0, v72:0, v73:0, v74:0, v75:0, v76:0, v77:0, v78:0, v79:0, v80:0, 3, 7, 4, 8) :|: v59:0 > 0 && v60:0 < v59:0 && v61:0 > 0 && v62:0 > 0 && v63:0 > 0 && v64:0 > 0 && v65:0 > 0 && v66:0 > 0 && v67:0 > 0 && v72:0 > 0 && v73:0 > 3 && v69:0 < 0 && v71:0 < v59:0 && v74:0 > 3 && v75:0 > 3 && v76:0 > 3 && v77:0 > 7 && v78:0 > 7 && v79:0 > 3 && v80:0 > 3 && v73:0 >= v72:0 && v74:0 >= v61:0 && v75:0 >= v62:0 && v76:0 >= v63:0 && v77:0 >= v64:0 && v78:0 >= v65:0 && v80:0 >= v67:0 && v79:0 >= v66:0
Filtered unneeded arguments:
   f_316(x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15, x16, x17, x18, x19, x20, x21, x22, x23, x24, x25, x26) -> f_316(x1, x2, x3, x4, x5, x6, x7, x8, x9, x11, x13, x14, x15, x16, x17, x18, x19, x20, x21, x22)
Removed division, modulo operations, cleaned up constraints. Obtained 1 rules.P rules:
f_316(v59:0, v60:0, v61:0, v62:0, v63:0, v64:0, v65:0, v66:0, v67:0, v69:0, v71:0, v72:0, v73:0, v74:0, v75:0, v76:0, v77:0, v78:0, v79:0, v80:0) -> f_316(v59:0, v60:0, v61:0, v62:0, v63:0, v64:0, v65:0, v66:0, v67:0, v71:0, v71:0 + v59:0, v72:0, v73:0, v74:0, v75:0, v76:0, v77:0, v78:0, v79:0, v80:0) :|: v60:0 < v59:0 && v59:0 > 0 && v61:0 > 0 && v62:0 > 0 && v63:0 > 0 && v64:0 > 0 && v65:0 > 0 && v66:0 > 0 && v67:0 > 0 && v72:0 > 0 && v73:0 > 3 && v69:0 < 0 && v71:0 < v59:0 && v74:0 > 3 && v75:0 > 3 && v76:0 > 3 && v77:0 > 7 && v78:0 > 7 && v79:0 > 3 && v80:0 > 3 && v73:0 >= v72:0 && v74:0 >= v61:0 && v75:0 >= v62:0 && v76:0 >= v63:0 && v77:0 >= v64:0 && v78:0 >= v65:0 && v79:0 >= v66:0 && v80:0 >= v67:0

----------------------------------------

(8)
Obligation:
Rules:
f_316(v59:0, v60:0, v61:0, v62:0, v63:0, v64:0, v65:0, v66:0, v67:0, v69:0, v71:0, v72:0, v73:0, v74:0, v75:0, v76:0, v77:0, v78:0, v79:0, v80:0) -> f_316(v59:0, v60:0, v61:0, v62:0, v63:0, v64:0, v65:0, v66:0, v67:0, v71:0, v71:0 + v59:0, v72:0, v73:0, v74:0, v75:0, v76:0, v77:0, v78:0, v79:0, v80:0) :|: v60:0 < v59:0 && v59:0 > 0 && v61:0 > 0 && v62:0 > 0 && v63:0 > 0 && v64:0 > 0 && v65:0 > 0 && v66:0 > 0 && v67:0 > 0 && v72:0 > 0 && v73:0 > 3 && v69:0 < 0 && v71:0 < v59:0 && v74:0 > 3 && v75:0 > 3 && v76:0 > 3 && v77:0 > 7 && v78:0 > 7 && v79:0 > 3 && v80:0 > 3 && v73:0 >= v72:0 && v74:0 >= v61:0 && v75:0 >= v62:0 && v76:0 >= v63:0 && v77:0 >= v64:0 && v78:0 >= v65:0 && v79:0 >= v66:0 && v80:0 >= v67:0

----------------------------------------

(9) IntTRSCompressionProof (EQUIVALENT)
Compressed rules.
----------------------------------------

(10)
Obligation:
Rules:
f_316(v59:0:0, v60:0:0, v61:0:0, v62:0:0, v63:0:0, v64:0:0, v65:0:0, v66:0:0, v67:0:0, v69:0:0, v71:0:0, v72:0:0, v73:0:0, v74:0:0, v75:0:0, v76:0:0, v77:0:0, v78:0:0, v79:0:0, v80:0:0) -> f_316(v59:0:0, v60:0:0, v61:0:0, v62:0:0, v63:0:0, v64:0:0, v65:0:0, v66:0:0, v67:0:0, v71:0:0, v71:0:0 + v59:0:0, v72:0:0, v73:0:0, v74:0:0, v75:0:0, v76:0:0, v77:0:0, v78:0:0, v79:0:0, v80:0:0) :|: v79:0:0 >= v66:0:0 && v80:0:0 >= v67:0:0 && v78:0:0 >= v65:0:0 && v77:0:0 >= v64:0:0 && v76:0:0 >= v63:0:0 && v75:0:0 >= v62:0:0 && v74:0:0 >= v61:0:0 && v73:0:0 >= v72:0:0 && v80:0:0 > 3 && v79:0:0 > 3 && v78:0:0 > 7 && v77:0:0 > 7 && v76:0:0 > 3 && v75:0:0 > 3 && v74:0:0 > 3 && v71:0:0 < v59:0:0 && v69:0:0 < 0 && v73:0:0 > 3 && v72:0:0 > 0 && v67:0:0 > 0 && v66:0:0 > 0 && v65:0:0 > 0 && v64:0:0 > 0 && v63:0:0 > 0 && v62:0:0 > 0 && v61:0:0 > 0 && v59:0:0 > 0 && v60:0:0 < v59:0:0

----------------------------------------

(11) RankingReductionPairProof (EQUIVALENT)
Interpretation:
[ f_316 ] = -1*f_316_11 + f_316_1

The following rules are decreasing:
f_316(v59:0:0, v60:0:0, v61:0:0, v62:0:0, v63:0:0, v64:0:0, v65:0:0, v66:0:0, v67:0:0, v69:0:0, v71:0:0, v72:0:0, v73:0:0, v74:0:0, v75:0:0, v76:0:0, v77:0:0, v78:0:0, v79:0:0, v80:0:0) -> f_316(v59:0:0, v60:0:0, v61:0:0, v62:0:0, v63:0:0, v64:0:0, v65:0:0, v66:0:0, v67:0:0, v71:0:0, v71:0:0 + v59:0:0, v72:0:0, v73:0:0, v74:0:0, v75:0:0, v76:0:0, v77:0:0, v78:0:0, v79:0:0, v80:0:0) :|: v79:0:0 >= v66:0:0 && v80:0:0 >= v67:0:0 && v78:0:0 >= v65:0:0 && v77:0:0 >= v64:0:0 && v76:0:0 >= v63:0:0 && v75:0:0 >= v62:0:0 && v74:0:0 >= v61:0:0 && v73:0:0 >= v72:0:0 && v80:0:0 > 3 && v79:0:0 > 3 && v78:0:0 > 7 && v77:0:0 > 7 && v76:0:0 > 3 && v75:0:0 > 3 && v74:0:0 > 3 && v71:0:0 < v59:0:0 && v69:0:0 < 0 && v73:0:0 > 3 && v72:0:0 > 0 && v67:0:0 > 0 && v66:0:0 > 0 && v65:0:0 > 0 && v64:0:0 > 0 && v63:0:0 > 0 && v62:0:0 > 0 && v61:0:0 > 0 && v59:0:0 > 0 && v60:0:0 < v59:0:0

The following rules are bounded:
f_316(v59:0:0, v60:0:0, v61:0:0, v62:0:0, v63:0:0, v64:0:0, v65:0:0, v66:0:0, v67:0:0, v69:0:0, v71:0:0, v72:0:0, v73:0:0, v74:0:0, v75:0:0, v76:0:0, v77:0:0, v78:0:0, v79:0:0, v80:0:0) -> f_316(v59:0:0, v60:0:0, v61:0:0, v62:0:0, v63:0:0, v64:0:0, v65:0:0, v66:0:0, v67:0:0, v71:0:0, v71:0:0 + v59:0:0, v72:0:0, v73:0:0, v74:0:0, v75:0:0, v76:0:0, v77:0:0, v78:0:0, v79:0:0, v80:0:0) :|: v79:0:0 >= v66:0:0 && v80:0:0 >= v67:0:0 && v78:0:0 >= v65:0:0 && v77:0:0 >= v64:0:0 && v76:0:0 >= v63:0:0 && v75:0:0 >= v62:0:0 && v74:0:0 >= v61:0:0 && v73:0:0 >= v72:0:0 && v80:0:0 > 3 && v79:0:0 > 3 && v78:0:0 > 7 && v77:0:0 > 7 && v76:0:0 > 3 && v75:0:0 > 3 && v74:0:0 > 3 && v71:0:0 < v59:0:0 && v69:0:0 < 0 && v73:0:0 > 3 && v72:0:0 > 0 && v67:0:0 > 0 && v66:0:0 > 0 && v65:0:0 > 0 && v64:0:0 > 0 && v63:0:0 > 0 && v62:0:0 > 0 && v61:0:0 > 0 && v59:0:0 > 0 && v60:0:0 < v59:0:0


----------------------------------------

(12)
YES