/export/starexec/sandbox2/solver/bin/starexec_run_termcomp17 /export/starexec/sandbox2/benchmark/theBenchmark.smt2 /export/starexec/sandbox2/output/output_files -------------------------------------------------------------------------------- NO Solver Timeout: 4 Global Timeout: 300 Maximum number of concurrent processes: 900 No parsing errors! Init Location: 0 Transitions: 0}> undef110, num^0 -> 0}> (0 + DName^0), num^0 -> (1 + num^0)}> 0}> (1 + i^0)}> undef372, a77^0 -> (0 + DName^0), a88^0 -> (0 + Pdoi^0), pc^0 -> 0, ret_IoCreateDevice1010^0 -> undef385, status^0 -> (0 + undef372), tmp99^0 -> undef390}> (0 + undef476), ___rho_2_^0 -> undef476, a11^0 -> (0 + lptNamei^0), b22^0 -> (0 + PdoType^0), c33^0 -> (0 + dcIdi^0), d44^0 -> (0 + num^0), ret_PPMakeDeviceName66^0 -> undef491, tmp55^0 -> undef494}> 0, unset^0 -> undef548}> Fresh variables: undef105, undef110, undef372, undef385, undef390, undef392, undef476, undef491, undef494, undef548, undef549, undef550, Undef variables: undef105, undef110, undef372, undef385, undef390, undef392, undef476, undef491, undef494, undef548, undef549, undef550, Abstraction variables: Exit nodes: Accepting locations: Asserts: Preprocessed LLVMGraph Init Location: 0 Transitions: (1 + i^0)}> 0, ___rho_1_^0 -> undef110, num^0 -> 0}> 0, ___rho_1_^0 -> undef110, num^0 -> 0}> 0, ___rho_1_^0 -> undef110, num^0 -> 0}> 0, ___rho_1_^0 -> undef110, num^0 -> 0}> 0, ___rho_1_^0 -> undef110, num^0 -> 0}> 0, ___rho_1_^0 -> undef110, num^0 -> 0}> undef110, num^0 -> 0}> undef110, num^0 -> 0}> undef110, num^0 -> 0}> undef110, num^0 -> 0}> Fresh variables: undef105, undef110, undef372, undef385, undef390, undef392, undef476, undef491, undef494, undef548, undef549, undef550, Undef variables: undef105, undef110, undef372, undef385, undef390, undef392, undef476, undef491, undef494, undef548, undef549, undef550, Abstraction variables: Exit nodes: Accepting locations: Asserts: ************************************************************* ******************************************************************************************* *********************** WORKING TRANSITION SYSTEM (DAG) *********************** ******************************************************************************************* Init Location: 0 Graph 0: Transitions: Variables: Graph 1: Transitions: 1 + i^0, rest remain the same}> Variables: Pdolen^0, i^0 Graph 2: Transitions: Variables: Precedence: Graph 0 Graph 1 Graph 2 0, ___rho_1_^0 -> undef110, num^0 -> 0, rest remain the same}> 0, ___rho_1_^0 -> undef110, num^0 -> 0, rest remain the same}> 0, ___rho_1_^0 -> undef110, num^0 -> 0, rest remain the same}> 0, ___rho_1_^0 -> undef110, num^0 -> 0, rest remain the same}> 0, ___rho_1_^0 -> undef110, num^0 -> 0, rest remain the same}> 0, ___rho_1_^0 -> undef110, num^0 -> 0, rest remain the same}> undef110, num^0 -> 0, rest remain the same}> undef110, num^0 -> 0, rest remain the same}> undef110, num^0 -> 0, rest remain the same}> undef110, num^0 -> 0, rest remain the same}> Map Locations to Subgraph: ( 0 , 0 ) ( 4 , 2 ) ( 11 , 1 ) ******************************************************************************************* ******************************** CHECKING ASSERTIONS ******************************** ******************************************************************************************* Proving termination of subgraph 0 Proving termination of subgraph 1 Checking unfeasibility... Time used: 0.002318 Checking conditional termination of SCC {l11}... LOG: CALL solveLinear LOG: RETURN solveLinear - Elapsed time: 0.001401s Ranking function: -1 + Pdolen^0 - i^0 New Graphs: Proving termination of subgraph 2 Checking unfeasibility... Time used: 0.004177 > No variable changes in termination graph. Checking conditional unfeasibility... Termination failed. Trying to show unreachability... Proving unreachability of entry: 0, ___rho_1_^0 -> undef110, num^0 -> 0, rest remain the same}> LOG: CALL check - Post:1 <= 0 - Process 1 * Exit transition: 0, ___rho_1_^0 -> undef110, num^0 -> 0, rest remain the same}> * Postcondition : 1 <= 0 Postcodition moved up: 1 <= 0 LOG: Try proving POST LOG: CALL check - Post:1 <= 0 - Process 2 * Exit transition: * Postcondition : 1 <= 0 LOG: CALL solveLinear LOG: RETURN solveLinear - Elapsed time: 0.001086s > Postcondition is not implied! LOG: RETURN check - Elapsed time: 0.001242s LOG: NarrowEntry size 1 It's unfeasible. Removing transition: 1 + i^0, rest remain the same}> ENTRIES: END ENTRIES: GRAPH: END GRAPH: EXIT: 0, ___rho_1_^0 -> undef110, num^0 -> 0, rest remain the same}> POST: 1 <= 0 LOG: Try proving POST [21256 : 21257] [21256 : 21258] [21256 : 21259] LOG: Postcondition is not implied - no solution > Postcondition is not implied! LOG: RETURN check - Elapsed time: 0.020039s Cannot prove unreachability [21256 : 21260] [21256 : 21261] Successful child: 21260 Program does NOT terminate