/export/starexec/sandbox/solver/bin/starexec_run_termcomp17 /export/starexec/sandbox/benchmark/theBenchmark.smt2 /export/starexec/sandbox/output/output_files -------------------------------------------------------------------------------- NO Solver Timeout: 4 Global Timeout: 300 Maximum number of concurrent processes: 900 No parsing errors! Init Location: 0 Transitions: (~(1) + i21^0)}> (16 + i21^0)}> ((0 + (~(1) * disp9^0)) + i6^0)}> (8 + (~(1) * hshift11^0)), hsize___019^0 -> undef377, hsize_reg10^0 -> undef379, i21^0 -> (~(16) + undef377), m122^0 -> ~(1)}> undef424, hshift11^0 -> (1 + hshift11^0)}> (~(16) + i29^0)}> (0 + undef557), fcode5^0 -> (0 + hsize^0), hshift11^0 -> 0, tmp12^0 -> undef557}> 429496}> (~(1) + InCnt^0), ret_getbyte18^0 -> undef706}> 429496}> (~(1) + apsim_InCnt^0), tmp___017^0 -> (0 + apsim_InCnt^0)}> 257}> 256}> (~(1) + bits33^0), c37^0 -> undef1027}> 2}> undef1281, offset^0 -> 0}> (1 + i45^0)}> 0, n44^0 -> undef1668}> undef1716}> (0 + maxmaxcode^0)}> 0, maxcode^0 -> undef1971, n_bits^0 -> 9}> (1 + n_bits^0)}> 0}> ((0 + bytes_out^0) + n_bits^0)}> (1 + i41^0)}> 0, n40^0 -> (0 + n_bits^0)}> 0}> undef3064, bytes_out^0 -> ((0 + undef3064) + bytes_out^0)}> ((0 + n_bits^0) + offset^0)}> (~(8) + bits33^0), code31^0 -> undef3479}> ((~(8) + bits33^0) + undef3661), code31^0 -> undef3632, r_off32^0 -> undef3661}> (0 + n_bits^0), clear_flg^0 -> 1, code31^0 -> 256, free_ent^0 -> 257, r_off32^0 -> (0 + offset^0)}> (~(1) + i29^0)}> (16 + i29^0)}> undef3968}> undef3999, i29^0 -> (~(16) + undef3999), m130^0 -> ~(1), ratio^0 -> 0}> (0 + rat26^0)}> 2147483647}> (0 + count^0), apsim_InCnt^0 -> 53, bytes_out^0 -> 3, checkpoint^0 -> 10000, clear_flg^0 -> 0, i6^0 -> 0, in_count^0 -> 1, maxbits^0 -> 16, maxcode^0 -> undef4266, maxmaxcode^0 -> undef4267, n_bits^0 -> 9, offset^0 -> 0, out_count^0 -> 0, ratio^0 -> 0}> (1 + i3^0), seed2^0 -> undef4329, tabort4^0 -> (0 + i3^0)}> undef4376}> undef4427}> (10000 + in_count^0)}> (1 + free_ent^0), tmp___115^0 -> (0 + free_ent^0)}> (0 + c7^0), out_count^0 -> (1 + out_count^0)}> (1 + apsim_bound11113^0)}> undef5165}> ((0 + hsize_reg10^0) + i6^0)}> 1}> ((0 + hsize_reg10^0) + (~(1) * i6^0))}> undef5675}> (0 + undef5862), fcode5^0 -> undef5830, i6^0 -> undef5842, in_count^0 -> (1 + in_count^0), tmp___014^0 -> undef5862}> 429496}> (~(1) + InCnt^0), ret_getbyte25^0 -> undef6011}> 429496}> (~(1) + apsim_InCnt^0), tmp___024^0 -> (0 + apsim_InCnt^0)}> 0}> (~(16) + i21^0)}> 50, i3^0 -> 0, seed2^0 -> 1}> Fresh variables: undef377, undef379, undef424, undef557, undef706, undef1027, undef1281, undef1668, undef1716, undef1971, undef3064, undef3479, undef3632, undef3661, undef3968, undef3999, undef4266, undef4267, undef4329, undef4376, undef4427, undef5165, undef5675, undef5830, undef5842, undef5862, undef6011, Undef variables: undef377, undef379, undef424, undef557, undef706, undef1027, undef1281, undef1668, undef1716, undef1971, undef3064, undef3479, undef3632, undef3661, undef3968, undef3999, undef4266, undef4267, undef4329, undef4376, undef4427, undef5165, undef5675, undef5830, undef5842, undef5862, undef6011, Abstraction variables: Exit nodes: Accepting locations: Asserts: Preprocessed LLVMGraph Init Location: 0 Transitions: (~(1) + apsim_InCnt^0), apsim_bound11113^0 -> 0, c7^0 -> (0 + undef5862), fcode5^0 -> undef5830, i6^0 -> undef5842, in_count^0 -> (1 + in_count^0), out_count^0 -> (1 + out_count^0)}> (~(1) + apsim_InCnt^0), apsim_bound11113^0 -> 0, c7^0 -> (0 + undef5862), disp9^0 -> ((0 + hsize_reg10^0) + (~(1) * undef5842)), fcode5^0 -> undef5830, i6^0 -> undef5842, in_count^0 -> (1 + in_count^0)}> (~(1) + apsim_InCnt^0), apsim_bound11113^0 -> 0, c7^0 -> (0 + undef5862), disp9^0 -> ((0 + hsize_reg10^0) + (~(1) * undef5842)), fcode5^0 -> undef5830, i6^0 -> undef5842, in_count^0 -> (1 + in_count^0)}> (~(1) + apsim_InCnt^0), apsim_bound11113^0 -> 0, c7^0 -> (0 + undef5862), disp9^0 -> 1, fcode5^0 -> undef5830, i6^0 -> undef5842, in_count^0 -> (1 + in_count^0)}> (~(1) + apsim_InCnt^0), apsim_bound11113^0 -> 0, c7^0 -> (0 + undef5862), fcode5^0 -> undef5830, i6^0 -> undef5842, in_count^0 -> (1 + in_count^0)}> (~(1) + apsim_InCnt^0), apsim_bound11113^0 -> 0, c7^0 -> (0 + undef5862), fcode5^0 -> undef5830, i6^0 -> undef5842, in_count^0 -> (1 + in_count^0), out_count^0 -> (1 + out_count^0)}> (~(1) + apsim_InCnt^0), apsim_bound11113^0 -> 0, c7^0 -> (0 + undef5862), disp9^0 -> ((0 + hsize_reg10^0) + (~(1) * undef5842)), fcode5^0 -> undef5830, i6^0 -> undef5842, in_count^0 -> (1 + in_count^0)}> (~(1) + apsim_InCnt^0), apsim_bound11113^0 -> 0, c7^0 -> (0 + undef5862), disp9^0 -> ((0 + hsize_reg10^0) + (~(1) * undef5842)), fcode5^0 -> undef5830, i6^0 -> undef5842, in_count^0 -> (1 + in_count^0)}> (~(1) + apsim_InCnt^0), apsim_bound11113^0 -> 0, c7^0 -> (0 + undef5862), disp9^0 -> 1, fcode5^0 -> undef5830, i6^0 -> undef5842, in_count^0 -> (1 + in_count^0)}> (~(1) + InCnt^0), apsim_InCnt^0 -> (~(1) + apsim_InCnt^0), apsim_bound11113^0 -> 0, c7^0 -> (0 + undef5862), fcode5^0 -> undef5830, i6^0 -> undef5842, in_count^0 -> (1 + in_count^0), out_count^0 -> (1 + out_count^0)}> (~(1) + InCnt^0), apsim_InCnt^0 -> (~(1) + apsim_InCnt^0), apsim_bound11113^0 -> 0, c7^0 -> (0 + undef5862), disp9^0 -> ((0 + hsize_reg10^0) + (~(1) * undef5842)), fcode5^0 -> undef5830, i6^0 -> undef5842, in_count^0 -> (1 + in_count^0)}> (~(1) + InCnt^0), apsim_InCnt^0 -> (~(1) + apsim_InCnt^0), apsim_bound11113^0 -> 0, c7^0 -> (0 + undef5862), disp9^0 -> ((0 + hsize_reg10^0) + (~(1) * undef5842)), fcode5^0 -> undef5830, i6^0 -> undef5842, in_count^0 -> (1 + in_count^0)}> (~(1) + InCnt^0), apsim_InCnt^0 -> (~(1) + apsim_InCnt^0), apsim_bound11113^0 -> 0, c7^0 -> (0 + undef5862), disp9^0 -> 1, fcode5^0 -> undef5830, i6^0 -> undef5842, in_count^0 -> (1 + in_count^0)}> (~(1) + InCnt^0), apsim_InCnt^0 -> (~(1) + apsim_InCnt^0), apsim_bound11113^0 -> 0, c7^0 -> (0 + undef5862), fcode5^0 -> undef5830, i6^0 -> undef5842, in_count^0 -> (1 + in_count^0)}> (~(1) + InCnt^0), apsim_InCnt^0 -> (~(1) + apsim_InCnt^0), apsim_bound11113^0 -> 0, c7^0 -> (0 + undef5862), fcode5^0 -> undef5830, i6^0 -> undef5842, in_count^0 -> (1 + in_count^0), out_count^0 -> (1 + out_count^0)}> (~(1) + InCnt^0), apsim_InCnt^0 -> (~(1) + apsim_InCnt^0), apsim_bound11113^0 -> 0, c7^0 -> (0 + undef5862), disp9^0 -> ((0 + hsize_reg10^0) + (~(1) * undef5842)), fcode5^0 -> undef5830, i6^0 -> undef5842, in_count^0 -> (1 + in_count^0)}> (~(1) + InCnt^0), apsim_InCnt^0 -> (~(1) + apsim_InCnt^0), apsim_bound11113^0 -> 0, c7^0 -> (0 + undef5862), disp9^0 -> ((0 + hsize_reg10^0) + (~(1) * undef5842)), fcode5^0 -> undef5830, i6^0 -> undef5842, in_count^0 -> (1 + in_count^0)}> (~(1) + InCnt^0), apsim_InCnt^0 -> (~(1) + apsim_InCnt^0), apsim_bound11113^0 -> 0, c7^0 -> (0 + undef5862), disp9^0 -> 1, fcode5^0 -> undef5830, i6^0 -> undef5842, in_count^0 -> (1 + in_count^0)}> (~(1) + i21^0)}> (16 + (~(16) + i21^0))}> (~(16) + i21^0)}> (1 + apsim_bound11113^0), i6^0 -> ((0 + (~(1) * disp9^0)) + i6^0), out_count^0 -> (1 + out_count^0)}> (1 + apsim_bound11113^0), i6^0 -> ((0 + (~(1) * disp9^0)) + i6^0)}> ((0 + (~(1) * disp9^0)) + i6^0), out_count^0 -> (1 + out_count^0)}> ((0 + (~(1) * disp9^0)) + i6^0)}> (1 + apsim_bound11113^0), i6^0 -> ((0 + (~(1) * disp9^0)) + i6^0), out_count^0 -> (1 + out_count^0)}> (1 + apsim_bound11113^0), i6^0 -> ((0 + (~(1) * disp9^0)) + i6^0)}> ((0 + (~(1) * disp9^0)) + i6^0), out_count^0 -> (1 + out_count^0)}> (1 + apsim_bound11113^0), i6^0 -> ((0 + hsize_reg10^0) + ((0 + (~(1) * disp9^0)) + i6^0)), out_count^0 -> (1 + out_count^0)}> (1 + apsim_bound11113^0), i6^0 -> ((0 + hsize_reg10^0) + ((0 + (~(1) * disp9^0)) + i6^0))}> ((0 + hsize_reg10^0) + ((0 + (~(1) * disp9^0)) + i6^0)), out_count^0 -> (1 + out_count^0)}> ((0 + hsize_reg10^0) + ((0 + (~(1) * disp9^0)) + i6^0))}> (1 + apsim_bound11113^0), i6^0 -> ((0 + hsize_reg10^0) + ((0 + (~(1) * disp9^0)) + i6^0)), out_count^0 -> (1 + out_count^0)}> (1 + apsim_bound11113^0), i6^0 -> ((0 + hsize_reg10^0) + ((0 + (~(1) * disp9^0)) + i6^0))}> ((0 + hsize_reg10^0) + ((0 + (~(1) * disp9^0)) + i6^0)), out_count^0 -> (1 + out_count^0)}> (8 + (~(1) * hshift11^0)), hsize_reg10^0 -> undef379, i21^0 -> (~(16) + undef377)}> undef424, hshift11^0 -> (1 + hshift11^0)}> (16 + (~(16) + i29^0))}> (~(16) + i29^0)}> undef3064, bytes_out^0 -> ((0 + undef3064) + bytes_out^0), clear_flg^0 -> 1, free_ent^0 -> 257, offset^0 -> ((0 + n_bits^0) + offset^0)}> ((~(8) + (0 + n_bits^0)) + undef3661), clear_flg^0 -> 1, free_ent^0 -> 257, offset^0 -> ((0 + n_bits^0) + offset^0)}> ((~(8) + (0 + n_bits^0)) + undef3661), clear_flg^0 -> 1, free_ent^0 -> 257, offset^0 -> ((0 + n_bits^0) + offset^0)}> undef3064, bytes_out^0 -> ((0 + undef3064) + bytes_out^0), clear_flg^0 -> 1, free_ent^0 -> 257, offset^0 -> ((0 + n_bits^0) + offset^0)}> ((~(8) + (0 + n_bits^0)) + undef3661), clear_flg^0 -> 1, free_ent^0 -> 257, offset^0 -> ((0 + n_bits^0) + offset^0)}> ((~(8) + (0 + n_bits^0)) + undef3661), clear_flg^0 -> 1, free_ent^0 -> 257, offset^0 -> ((0 + n_bits^0) + offset^0)}> undef3064, bytes_out^0 -> ((0 + undef3064) + bytes_out^0), clear_flg^0 -> 1, free_ent^0 -> 257, offset^0 -> ((0 + n_bits^0) + offset^0)}> ((~(8) + (0 + n_bits^0)) + undef3661), clear_flg^0 -> 1, free_ent^0 -> 257, offset^0 -> ((0 + n_bits^0) + offset^0)}> ((~(8) + (0 + n_bits^0)) + undef3661), clear_flg^0 -> 1, free_ent^0 -> 257, offset^0 -> ((0 + n_bits^0) + offset^0)}> undef3064, bytes_out^0 -> ((0 + undef3064) + bytes_out^0), clear_flg^0 -> 1, free_ent^0 -> 257, offset^0 -> ((0 + n_bits^0) + offset^0)}> (~(8) + ((~(8) + (0 + n_bits^0)) + undef3661)), clear_flg^0 -> 1, free_ent^0 -> 257, offset^0 -> ((0 + n_bits^0) + offset^0)}> (~(8) + ((~(8) + (0 + n_bits^0)) + undef3661)), clear_flg^0 -> 1, free_ent^0 -> 257, offset^0 -> ((0 + n_bits^0) + offset^0)}> undef3064, bytes_out^0 -> ((0 + undef3064) + bytes_out^0), clear_flg^0 -> 1, free_ent^0 -> 257, offset^0 -> ((0 + n_bits^0) + offset^0)}> (~(8) + ((~(8) + (0 + n_bits^0)) + undef3661)), clear_flg^0 -> 1, free_ent^0 -> 257, offset^0 -> ((0 + n_bits^0) + offset^0)}> (~(8) + ((~(8) + (0 + n_bits^0)) + undef3661)), clear_flg^0 -> 1, free_ent^0 -> 257, offset^0 -> ((0 + n_bits^0) + offset^0)}> (~(1) + i29^0)}> (~(1) + bits33^0), offset^0 -> 0}> (~(1) + bits33^0), offset^0 -> 0}> (~(1) + bits33^0), offset^0 -> 0}> (~(1) + bits33^0)}> (~(1) + bits33^0), offset^0 -> 0}> (~(1) + bits33^0), offset^0 -> 0}> (~(1) + bits33^0), offset^0 -> 0}> (~(1) + bits33^0)}> (~(1) + bits33^0), offset^0 -> 0}> (~(1) + bits33^0), offset^0 -> 0}> (~(1) + bits33^0), offset^0 -> 0}> ((0 + bytes_out^0) + n_bits^0), maxcode^0 -> undef1716, n_bits^0 -> (1 + n_bits^0), offset^0 -> 0}> ((0 + bytes_out^0) + n_bits^0), maxcode^0 -> undef1716, n_bits^0 -> (1 + n_bits^0), offset^0 -> 0}> ((0 + bytes_out^0) + n_bits^0), maxcode^0 -> (0 + maxmaxcode^0), n_bits^0 -> (1 + n_bits^0), offset^0 -> 0}> ((0 + bytes_out^0) + n_bits^0), clear_flg^0 -> 0, maxcode^0 -> undef1971, n_bits^0 -> 9, offset^0 -> 0}> ((0 + bytes_out^0) + n_bits^0), clear_flg^0 -> 0, maxcode^0 -> undef1971, n_bits^0 -> 9, offset^0 -> 0}> ((0 + bytes_out^0) + n_bits^0), maxcode^0 -> undef1716, n_bits^0 -> (1 + n_bits^0), offset^0 -> 0}> ((0 + bytes_out^0) + n_bits^0), maxcode^0 -> undef1716, n_bits^0 -> (1 + n_bits^0), offset^0 -> 0}> ((0 + bytes_out^0) + n_bits^0), maxcode^0 -> (0 + maxmaxcode^0), n_bits^0 -> (1 + n_bits^0), offset^0 -> 0}> ((0 + bytes_out^0) + n_bits^0), clear_flg^0 -> 0, maxcode^0 -> undef1971, n_bits^0 -> 9, offset^0 -> 0}> ((0 + bytes_out^0) + n_bits^0), clear_flg^0 -> 0, maxcode^0 -> undef1971, n_bits^0 -> 9, offset^0 -> 0}> (1 + i41^0)}> undef1716, n_bits^0 -> (1 + n_bits^0), offset^0 -> 0}> undef1716, n_bits^0 -> (1 + n_bits^0), offset^0 -> 0}> (0 + maxmaxcode^0), n_bits^0 -> (1 + n_bits^0), offset^0 -> 0}> 0, maxcode^0 -> undef1971, n_bits^0 -> 9, offset^0 -> 0}> 0, maxcode^0 -> undef1971, n_bits^0 -> 9, offset^0 -> 0}> 0, n40^0 -> (0 + n_bits^0)}> (~(1) + (0 + 50)), apsim_InCnt^0 -> (~(1) + 53), bytes_out^0 -> 3, checkpoint^0 -> 10000, clear_flg^0 -> 0, fcode5^0 -> (0 + hsize^0), free_ent^0 -> 256, hshift11^0 -> 0, i6^0 -> 0, in_count^0 -> 1, maxbits^0 -> 16, maxcode^0 -> undef4266, maxmaxcode^0 -> undef4267, n_bits^0 -> 9, offset^0 -> 0, out_count^0 -> 0, ratio^0 -> 0}> (~(1) + (0 + 50)), apsim_InCnt^0 -> (~(1) + 53), bytes_out^0 -> 3, checkpoint^0 -> 10000, clear_flg^0 -> 0, fcode5^0 -> (0 + hsize^0), free_ent^0 -> 257, hshift11^0 -> 0, i6^0 -> 0, in_count^0 -> 1, maxbits^0 -> 16, maxcode^0 -> undef4266, maxmaxcode^0 -> undef4267, n_bits^0 -> 9, offset^0 -> 0, out_count^0 -> 0, ratio^0 -> 0}> (~(1) + (0 + 50)), apsim_InCnt^0 -> (~(1) + 53), bytes_out^0 -> 3, checkpoint^0 -> 10000, clear_flg^0 -> 0, fcode5^0 -> (0 + hsize^0), free_ent^0 -> 257, hshift11^0 -> 0, i6^0 -> 0, in_count^0 -> 1, maxbits^0 -> 16, maxcode^0 -> undef4266, maxmaxcode^0 -> undef4267, n_bits^0 -> 9, offset^0 -> 0, out_count^0 -> 0, ratio^0 -> 0}> (1 + i3^0)}> (10000 + in_count^0), i29^0 -> (~(16) + undef3999), rat26^0 -> undef4376, ratio^0 -> 0}> (10000 + in_count^0), rat26^0 -> undef4376, ratio^0 -> (0 + undef4376)}> (10000 + in_count^0), i29^0 -> (~(16) + undef3999), rat26^0 -> undef3968, ratio^0 -> 0}> (10000 + in_count^0), rat26^0 -> undef3968, ratio^0 -> (0 + undef3968)}> (10000 + in_count^0), i29^0 -> (~(16) + undef3999), rat26^0 -> undef3968, ratio^0 -> 0}> (10000 + in_count^0), rat26^0 -> undef3968, ratio^0 -> (0 + undef3968)}> (10000 + in_count^0), i29^0 -> (~(16) + undef3999), rat26^0 -> 2147483647, ratio^0 -> 0}> (10000 + in_count^0), rat26^0 -> 2147483647, ratio^0 -> (0 + 2147483647)}> (10000 + in_count^0), i29^0 -> (~(16) + undef3999), rat26^0 -> undef4376, ratio^0 -> 0}> (10000 + in_count^0), rat26^0 -> undef4376, ratio^0 -> (0 + undef4376)}> (10000 + in_count^0), i29^0 -> (~(16) + undef3999), rat26^0 -> undef3968, ratio^0 -> 0}> (10000 + in_count^0), rat26^0 -> undef3968, ratio^0 -> (0 + undef3968)}> (10000 + in_count^0), i29^0 -> (~(16) + undef3999), rat26^0 -> undef3968, ratio^0 -> 0}> (10000 + in_count^0), rat26^0 -> undef3968, ratio^0 -> (0 + undef3968)}> (10000 + in_count^0), i29^0 -> (~(16) + undef3999), rat26^0 -> 2147483647, ratio^0 -> 0}> (10000 + in_count^0), rat26^0 -> 2147483647, ratio^0 -> (0 + 2147483647)}> (1 + free_ent^0)}> Fresh variables: undef377, undef379, undef424, undef557, undef706, undef1027, undef1281, undef1668, undef1716, undef1971, undef3064, undef3479, undef3632, undef3661, undef3968, undef3999, undef4266, undef4267, undef4329, undef4376, undef4427, undef5165, undef5675, undef5830, undef5842, undef5862, undef6011, Undef variables: undef377, undef379, undef424, undef557, undef706, undef1027, undef1281, undef1668, undef1716, undef1971, undef3064, undef3479, undef3632, undef3661, undef3968, undef3999, undef4266, undef4267, undef4329, undef4376, undef4427, undef5165, undef5675, undef5830, undef5842, undef5862, undef6011, Abstraction variables: Exit nodes: Accepting locations: Asserts: ************************************************************* ******************************************************************************************* *********************** WORKING TRANSITION SYSTEM (DAG) *********************** ******************************************************************************************* Init Location: 0 Graph 0: Transitions: Variables: Graph 1: Transitions: 1 + i3^0, rest remain the same}> Variables: i3^0 Graph 2: Transitions: undef424, hshift11^0 -> 1 + hshift11^0, rest remain the same}> Variables: fcode5^0, hshift11^0 Graph 3: Transitions: -16 + i21^0, rest remain the same}> Variables: i21^0 Graph 4: Transitions: -1 + i21^0, rest remain the same}> Variables: i21^0 Graph 5: Transitions: -1 + apsim_InCnt^0, apsim_bound11113^0 -> 0, c7^0 -> undef5862, fcode5^0 -> undef5830, i6^0 -> undef5842, in_count^0 -> 1 + in_count^0, out_count^0 -> 1 + out_count^0, rest remain the same}> -1 + apsim_InCnt^0, apsim_bound11113^0 -> 0, c7^0 -> undef5862, disp9^0 -> hsize_reg10^0 - undef5842, fcode5^0 -> undef5830, i6^0 -> undef5842, in_count^0 -> 1 + in_count^0, rest remain the same}> -1 + apsim_InCnt^0, apsim_bound11113^0 -> 0, c7^0 -> undef5862, disp9^0 -> hsize_reg10^0 - undef5842, fcode5^0 -> undef5830, i6^0 -> undef5842, in_count^0 -> 1 + in_count^0, rest remain the same}> -1 + apsim_InCnt^0, apsim_bound11113^0 -> 0, c7^0 -> undef5862, disp9^0 -> 1, fcode5^0 -> undef5830, i6^0 -> undef5842, in_count^0 -> 1 + in_count^0, rest remain the same}> -1 + apsim_InCnt^0, apsim_bound11113^0 -> 0, c7^0 -> undef5862, fcode5^0 -> undef5830, i6^0 -> undef5842, in_count^0 -> 1 + in_count^0, rest remain the same}> -1 + apsim_InCnt^0, apsim_bound11113^0 -> 0, c7^0 -> undef5862, fcode5^0 -> undef5830, i6^0 -> undef5842, in_count^0 -> 1 + in_count^0, out_count^0 -> 1 + out_count^0, rest remain the same}> -1 + apsim_InCnt^0, apsim_bound11113^0 -> 0, c7^0 -> undef5862, disp9^0 -> hsize_reg10^0 - undef5842, fcode5^0 -> undef5830, i6^0 -> undef5842, in_count^0 -> 1 + in_count^0, rest remain the same}> -1 + apsim_InCnt^0, apsim_bound11113^0 -> 0, c7^0 -> undef5862, disp9^0 -> hsize_reg10^0 - undef5842, fcode5^0 -> undef5830, i6^0 -> undef5842, in_count^0 -> 1 + in_count^0, rest remain the same}> -1 + apsim_InCnt^0, apsim_bound11113^0 -> 0, c7^0 -> undef5862, disp9^0 -> 1, fcode5^0 -> undef5830, i6^0 -> undef5842, in_count^0 -> 1 + in_count^0, rest remain the same}> -1 + InCnt^0, apsim_InCnt^0 -> -1 + apsim_InCnt^0, apsim_bound11113^0 -> 0, c7^0 -> undef5862, fcode5^0 -> undef5830, i6^0 -> undef5842, in_count^0 -> 1 + in_count^0, out_count^0 -> 1 + out_count^0, rest remain the same}> -1 + InCnt^0, apsim_InCnt^0 -> -1 + apsim_InCnt^0, apsim_bound11113^0 -> 0, c7^0 -> undef5862, disp9^0 -> hsize_reg10^0 - undef5842, fcode5^0 -> undef5830, i6^0 -> undef5842, in_count^0 -> 1 + in_count^0, rest remain the same}> -1 + InCnt^0, apsim_InCnt^0 -> -1 + apsim_InCnt^0, apsim_bound11113^0 -> 0, c7^0 -> undef5862, disp9^0 -> hsize_reg10^0 - undef5842, fcode5^0 -> undef5830, i6^0 -> undef5842, in_count^0 -> 1 + in_count^0, rest remain the same}> -1 + InCnt^0, apsim_InCnt^0 -> -1 + apsim_InCnt^0, apsim_bound11113^0 -> 0, c7^0 -> undef5862, disp9^0 -> 1, fcode5^0 -> undef5830, i6^0 -> undef5842, in_count^0 -> 1 + in_count^0, rest remain the same}> -1 + InCnt^0, apsim_InCnt^0 -> -1 + apsim_InCnt^0, apsim_bound11113^0 -> 0, c7^0 -> undef5862, fcode5^0 -> undef5830, i6^0 -> undef5842, in_count^0 -> 1 + in_count^0, rest remain the same}> -1 + InCnt^0, apsim_InCnt^0 -> -1 + apsim_InCnt^0, apsim_bound11113^0 -> 0, c7^0 -> undef5862, fcode5^0 -> undef5830, i6^0 -> undef5842, in_count^0 -> 1 + in_count^0, out_count^0 -> 1 + out_count^0, rest remain the same}> -1 + InCnt^0, apsim_InCnt^0 -> -1 + apsim_InCnt^0, apsim_bound11113^0 -> 0, c7^0 -> undef5862, disp9^0 -> hsize_reg10^0 - undef5842, fcode5^0 -> undef5830, i6^0 -> undef5842, in_count^0 -> 1 + in_count^0, rest remain the same}> -1 + InCnt^0, apsim_InCnt^0 -> -1 + apsim_InCnt^0, apsim_bound11113^0 -> 0, c7^0 -> undef5862, disp9^0 -> hsize_reg10^0 - undef5842, fcode5^0 -> undef5830, i6^0 -> undef5842, in_count^0 -> 1 + in_count^0, rest remain the same}> -1 + InCnt^0, apsim_InCnt^0 -> -1 + apsim_InCnt^0, apsim_bound11113^0 -> 0, c7^0 -> undef5862, disp9^0 -> 1, fcode5^0 -> undef5830, i6^0 -> undef5842, in_count^0 -> 1 + in_count^0, rest remain the same}> 1 + apsim_bound11113^0, i6^0 -> -disp9^0 + i6^0, out_count^0 -> 1 + out_count^0, rest remain the same}> 1 + apsim_bound11113^0, i6^0 -> -disp9^0 + i6^0, rest remain the same}> -disp9^0 + i6^0, out_count^0 -> 1 + out_count^0, rest remain the same}> -disp9^0 + i6^0, rest remain the same}> 1 + apsim_bound11113^0, i6^0 -> -disp9^0 + i6^0, out_count^0 -> 1 + out_count^0, rest remain the same}> 1 + apsim_bound11113^0, i6^0 -> -disp9^0 + i6^0, rest remain the same}> -disp9^0 + i6^0, out_count^0 -> 1 + out_count^0, rest remain the same}> 1 + apsim_bound11113^0, i6^0 -> -disp9^0 + hsize_reg10^0 + i6^0, out_count^0 -> 1 + out_count^0, rest remain the same}> 1 + apsim_bound11113^0, i6^0 -> -disp9^0 + hsize_reg10^0 + i6^0, rest remain the same}> -disp9^0 + hsize_reg10^0 + i6^0, out_count^0 -> 1 + out_count^0, rest remain the same}> -disp9^0 + hsize_reg10^0 + i6^0, rest remain the same}> 1 + apsim_bound11113^0, i6^0 -> -disp9^0 + hsize_reg10^0 + i6^0, out_count^0 -> 1 + out_count^0, rest remain the same}> 1 + apsim_bound11113^0, i6^0 -> -disp9^0 + hsize_reg10^0 + i6^0, rest remain the same}> -disp9^0 + hsize_reg10^0 + i6^0, out_count^0 -> 1 + out_count^0, rest remain the same}> -16 + i29^0, rest remain the same}> undef3064, bytes_out^0 -> bytes_out^0 + undef3064, clear_flg^0 -> 1, free_ent^0 -> 257, offset^0 -> n_bits^0 + offset^0, rest remain the same}> -8 + n_bits^0 + undef3661, clear_flg^0 -> 1, free_ent^0 -> 257, offset^0 -> n_bits^0 + offset^0, rest remain the same}> -8 + n_bits^0 + undef3661, clear_flg^0 -> 1, free_ent^0 -> 257, offset^0 -> n_bits^0 + offset^0, rest remain the same}> undef3064, bytes_out^0 -> bytes_out^0 + undef3064, clear_flg^0 -> 1, free_ent^0 -> 257, offset^0 -> n_bits^0 + offset^0, rest remain the same}> -8 + n_bits^0 + undef3661, clear_flg^0 -> 1, free_ent^0 -> 257, offset^0 -> n_bits^0 + offset^0, rest remain the same}> -8 + n_bits^0 + undef3661, clear_flg^0 -> 1, free_ent^0 -> 257, offset^0 -> n_bits^0 + offset^0, rest remain the same}> undef3064, bytes_out^0 -> bytes_out^0 + undef3064, clear_flg^0 -> 1, free_ent^0 -> 257, offset^0 -> n_bits^0 + offset^0, rest remain the same}> -8 + n_bits^0 + undef3661, clear_flg^0 -> 1, free_ent^0 -> 257, offset^0 -> n_bits^0 + offset^0, rest remain the same}> -8 + n_bits^0 + undef3661, clear_flg^0 -> 1, free_ent^0 -> 257, offset^0 -> n_bits^0 + offset^0, rest remain the same}> undef3064, bytes_out^0 -> bytes_out^0 + undef3064, clear_flg^0 -> 1, free_ent^0 -> 257, offset^0 -> n_bits^0 + offset^0, rest remain the same}> -16 + n_bits^0 + undef3661, clear_flg^0 -> 1, free_ent^0 -> 257, offset^0 -> n_bits^0 + offset^0, rest remain the same}> -16 + n_bits^0 + undef3661, clear_flg^0 -> 1, free_ent^0 -> 257, offset^0 -> n_bits^0 + offset^0, rest remain the same}> undef3064, bytes_out^0 -> bytes_out^0 + undef3064, clear_flg^0 -> 1, free_ent^0 -> 257, offset^0 -> n_bits^0 + offset^0, rest remain the same}> -16 + n_bits^0 + undef3661, clear_flg^0 -> 1, free_ent^0 -> 257, offset^0 -> n_bits^0 + offset^0, rest remain the same}> -16 + n_bits^0 + undef3661, clear_flg^0 -> 1, free_ent^0 -> 257, offset^0 -> n_bits^0 + offset^0, rest remain the same}> -1 + i29^0, rest remain the same}> -1 + bits33^0, offset^0 -> 0, rest remain the same}> -1 + bits33^0, offset^0 -> 0, rest remain the same}> -1 + bits33^0, offset^0 -> 0, rest remain the same}> -1 + bits33^0, rest remain the same}> -1 + bits33^0, offset^0 -> 0, rest remain the same}> -1 + bits33^0, offset^0 -> 0, rest remain the same}> -1 + bits33^0, offset^0 -> 0, rest remain the same}> -1 + bits33^0, rest remain the same}> -1 + bits33^0, offset^0 -> 0, rest remain the same}> -1 + bits33^0, offset^0 -> 0, rest remain the same}> -1 + bits33^0, offset^0 -> 0, rest remain the same}> bytes_out^0 + n_bits^0, maxcode^0 -> undef1716, n_bits^0 -> 1 + n_bits^0, offset^0 -> 0, rest remain the same}> bytes_out^0 + n_bits^0, maxcode^0 -> undef1716, n_bits^0 -> 1 + n_bits^0, offset^0 -> 0, rest remain the same}> bytes_out^0 + n_bits^0, maxcode^0 -> maxmaxcode^0, n_bits^0 -> 1 + n_bits^0, offset^0 -> 0, rest remain the same}> bytes_out^0 + n_bits^0, clear_flg^0 -> 0, maxcode^0 -> undef1971, n_bits^0 -> 9, offset^0 -> 0, rest remain the same}> bytes_out^0 + n_bits^0, clear_flg^0 -> 0, maxcode^0 -> undef1971, n_bits^0 -> 9, offset^0 -> 0, rest remain the same}> bytes_out^0 + n_bits^0, maxcode^0 -> undef1716, n_bits^0 -> 1 + n_bits^0, offset^0 -> 0, rest remain the same}> bytes_out^0 + n_bits^0, maxcode^0 -> undef1716, n_bits^0 -> 1 + n_bits^0, offset^0 -> 0, rest remain the same}> bytes_out^0 + n_bits^0, maxcode^0 -> maxmaxcode^0, n_bits^0 -> 1 + n_bits^0, offset^0 -> 0, rest remain the same}> bytes_out^0 + n_bits^0, clear_flg^0 -> 0, maxcode^0 -> undef1971, n_bits^0 -> 9, offset^0 -> 0, rest remain the same}> bytes_out^0 + n_bits^0, clear_flg^0 -> 0, maxcode^0 -> undef1971, n_bits^0 -> 9, offset^0 -> 0, rest remain the same}> 1 + i41^0, rest remain the same}> undef1716, n_bits^0 -> 1 + n_bits^0, offset^0 -> 0, rest remain the same}> undef1716, n_bits^0 -> 1 + n_bits^0, offset^0 -> 0, rest remain the same}> maxmaxcode^0, n_bits^0 -> 1 + n_bits^0, offset^0 -> 0, rest remain the same}> 0, maxcode^0 -> undef1971, n_bits^0 -> 9, offset^0 -> 0, rest remain the same}> 0, maxcode^0 -> undef1971, n_bits^0 -> 9, offset^0 -> 0, rest remain the same}> 0, n40^0 -> n_bits^0, rest remain the same}> 10000 + in_count^0, i29^0 -> -16 + undef3999, rat26^0 -> undef4376, ratio^0 -> 0, rest remain the same}> 10000 + in_count^0, rat26^0 -> undef4376, ratio^0 -> undef4376, rest remain the same}> 10000 + in_count^0, i29^0 -> -16 + undef3999, rat26^0 -> undef3968, ratio^0 -> 0, rest remain the same}> 10000 + in_count^0, rat26^0 -> undef3968, ratio^0 -> undef3968, rest remain the same}> 10000 + in_count^0, i29^0 -> -16 + undef3999, rat26^0 -> undef3968, ratio^0 -> 0, rest remain the same}> 10000 + in_count^0, rat26^0 -> undef3968, ratio^0 -> undef3968, rest remain the same}> 10000 + in_count^0, i29^0 -> -16 + undef3999, rat26^0 -> 2147483647, ratio^0 -> 0, rest remain the same}> 10000 + in_count^0, rat26^0 -> 2147483647, ratio^0 -> 2147483647, rest remain the same}> 10000 + in_count^0, i29^0 -> -16 + undef3999, rat26^0 -> undef4376, ratio^0 -> 0, rest remain the same}> 10000 + in_count^0, rat26^0 -> undef4376, ratio^0 -> undef4376, rest remain the same}> 10000 + in_count^0, i29^0 -> -16 + undef3999, rat26^0 -> undef3968, ratio^0 -> 0, rest remain the same}> 10000 + in_count^0, rat26^0 -> undef3968, ratio^0 -> undef3968, rest remain the same}> 10000 + in_count^0, i29^0 -> -16 + undef3999, rat26^0 -> undef3968, ratio^0 -> 0, rest remain the same}> 10000 + in_count^0, rat26^0 -> undef3968, ratio^0 -> undef3968, rest remain the same}> 10000 + in_count^0, i29^0 -> -16 + undef3999, rat26^0 -> 2147483647, ratio^0 -> 0, rest remain the same}> 10000 + in_count^0, rat26^0 -> 2147483647, ratio^0 -> 2147483647, rest remain the same}> 1 + free_ent^0, rest remain the same}> Variables: InCnt^0, apsim_InCnt^0, c7^0, fcode5^0, i6^0, in_count^0, out_count^0, disp9^0, hsize_reg10^0, apsim_bound11113^0, i29^0, bits33^0, bytes_out^0, n_bits^0, offset^0, maxcode^0, clear_flg^0, free_ent^0, i41^0, maxbits^0, n40^0, maxmaxcode^0, checkpoint^0, block_compress^0, hsize^0, rat26^0, ratio^0 Graph 6: Transitions: Variables: Precedence: Graph 0 Graph 1 Graph 2 49, apsim_InCnt^0 -> 52, bytes_out^0 -> 3, checkpoint^0 -> 10000, clear_flg^0 -> 0, fcode5^0 -> hsize^0, free_ent^0 -> 256, hshift11^0 -> 0, i6^0 -> 0, in_count^0 -> 1, maxbits^0 -> 16, maxcode^0 -> undef4266, maxmaxcode^0 -> undef4267, n_bits^0 -> 9, offset^0 -> 0, out_count^0 -> 0, ratio^0 -> 0, rest remain the same}> 49, apsim_InCnt^0 -> 52, bytes_out^0 -> 3, checkpoint^0 -> 10000, clear_flg^0 -> 0, fcode5^0 -> hsize^0, free_ent^0 -> 257, hshift11^0 -> 0, i6^0 -> 0, in_count^0 -> 1, maxbits^0 -> 16, maxcode^0 -> undef4266, maxmaxcode^0 -> undef4267, n_bits^0 -> 9, offset^0 -> 0, out_count^0 -> 0, ratio^0 -> 0, rest remain the same}> 49, apsim_InCnt^0 -> 52, bytes_out^0 -> 3, checkpoint^0 -> 10000, clear_flg^0 -> 0, fcode5^0 -> hsize^0, free_ent^0 -> 257, hshift11^0 -> 0, i6^0 -> 0, in_count^0 -> 1, maxbits^0 -> 16, maxcode^0 -> undef4266, maxmaxcode^0 -> undef4267, n_bits^0 -> 9, offset^0 -> 0, out_count^0 -> 0, ratio^0 -> 0, rest remain the same}> Graph 3 8 - hshift11^0, hsize_reg10^0 -> undef379, i21^0 -> -16 + undef377, rest remain the same}> Graph 4 Graph 5 Graph 6 Map Locations to Subgraph: ( 0 , 0 ) ( 2 , 5 ) ( 3 , 4 ) ( 5 , 3 ) ( 7 , 5 ) ( 10 , 2 ) ( 11 , 5 ) ( 14 , 5 ) ( 20 , 5 ) ( 22 , 5 ) ( 25 , 6 ) ( 42 , 5 ) ( 57 , 1 ) ( 62 , 5 ) ******************************************************************************************* ******************************** CHECKING ASSERTIONS ******************************** ******************************************************************************************* Proving termination of subgraph 0 Proving termination of subgraph 1 Checking unfeasibility... Time used: 0.001895 Checking conditional termination of SCC {l57}... LOG: CALL solveLinear LOG: RETURN solveLinear - Elapsed time: 0.003721s Ranking function: 49 - i3^0 New Graphs: Proving termination of subgraph 2 Checking unfeasibility... Time used: 0.002697 Checking conditional termination of SCC {l10}... LOG: CALL solveLinear LOG: RETURN solveLinear - Elapsed time: 0.000751s LOG: CALL solveLinear LOG: RETURN solveLinear - Elapsed time: 0.001741s [9768 : 9769] [9768 : 9770] Solving with 1 template(s). LOG: CALL solveNonLinearGetFirstSolution LOG: RETURN solveNonLinearGetFirstSolution - Elapsed time: 0.011691s Time used: 0.011339 Improving Solution with cost 1 ... LOG: CALL solveNonLinearGetNextSolution LOG: RETURN solveNonLinearGetNextSolution - Elapsed time: 1.001189s Time used: 1.0012 LOG: SAT solveNonLinear - Elapsed time: 1.012880s Cost: 1; Total time: 1.01254 Quasi-ranking function: 50000 - hshift11^0 New Graphs: Transitions: undef424, hshift11^0 -> 1 + hshift11^0, rest remain the same}> Variables: fcode5^0, hshift11^0 Checking conditional termination of SCC {l10}... LOG: CALL solveLinear LOG: RETURN solveLinear - Elapsed time: 0.000797s LOG: CALL solveLinear LOG: RETURN solveLinear - Elapsed time: 0.002280s [9768 : 9774] [9768 : 9775] Solving with 1 template(s). LOG: CALL solveNonLinearGetFirstSolution LOG: RETURN solveNonLinearGetFirstSolution - Elapsed time: 4.102911s Time used: 4.1022 Termination failed. Trying to show unreachability... Proving unreachability of entry: 49, apsim_InCnt^0 -> 52, bytes_out^0 -> 3, checkpoint^0 -> 10000, clear_flg^0 -> 0, fcode5^0 -> hsize^0, free_ent^0 -> 256, hshift11^0 -> 0, i6^0 -> 0, in_count^0 -> 1, maxbits^0 -> 16, maxcode^0 -> undef4266, maxmaxcode^0 -> undef4267, n_bits^0 -> 9, offset^0 -> 0, out_count^0 -> 0, ratio^0 -> 0, rest remain the same}> LOG: CALL check - Post:1 <= 0 - Process 1 * Exit transition: 49, apsim_InCnt^0 -> 52, bytes_out^0 -> 3, checkpoint^0 -> 10000, clear_flg^0 -> 0, fcode5^0 -> hsize^0, free_ent^0 -> 256, hshift11^0 -> 0, i6^0 -> 0, in_count^0 -> 1, maxbits^0 -> 16, maxcode^0 -> undef4266, maxmaxcode^0 -> undef4267, n_bits^0 -> 9, offset^0 -> 0, out_count^0 -> 0, ratio^0 -> 0, rest remain the same}> * Postcondition : 1 <= 0 Postcodition moved up: 1 <= 0 LOG: Try proving POST LOG: CALL check - Post:1 <= 0 - Process 2 * Exit transition: * Postcondition : 1 <= 0 LOG: CALL solveLinear LOG: RETURN solveLinear - Elapsed time: 0.002653s > Postcondition is not implied! LOG: RETURN check - Elapsed time: 0.002741s LOG: NarrowEntry size 1 Narrowing transition: 1 + i3^0, rest remain the same}> LOG: Narrow transition size 1 ENTRIES: END ENTRIES: GRAPH: 1 + i3^0, rest remain the same}> END GRAPH: EXIT: 49, apsim_InCnt^0 -> 52, bytes_out^0 -> 3, checkpoint^0 -> 10000, clear_flg^0 -> 0, fcode5^0 -> hsize^0, free_ent^0 -> 256, hshift11^0 -> 0, i6^0 -> 0, in_count^0 -> 1, maxbits^0 -> 16, maxcode^0 -> undef4266, maxmaxcode^0 -> undef4267, n_bits^0 -> 9, offset^0 -> 0, out_count^0 -> 0, ratio^0 -> 0, rest remain the same}> POST: 1 <= 0 LOG: Try proving POST [9768 : 9779] [9768 : 9780] [9768 : 9781] LOG: Postcondition is not implied - no solution > Postcondition is not implied! LOG: RETURN check - Elapsed time: 1.056152s Cannot prove unreachability [9768 : 9782] [9768 : 9786] Successful child: 9782 Program does NOT terminate